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Edited to clarify some questions

I’m working on a design that will take a 0.5V-4V signal from a laser displacement sensor (Keyence Il-1000) and convert it to a frequency signal (0.1-2Mhz) for input to an FPGA counter. The sensor needs 10-30v so I am powering it with a 24v switching power supply.

My board is plugged into the daughterboard header on of an FPGA board. This header has 5v and ground pins, which I use to power the AD7741 V/F converter. The FPGA and V/F converter are powered by 5v supply. My board also has 24v supplied by screw terminals. The two power supply grounds are joined at the PSU

I have a “working” circuit with an Analog Devices AD7741 V/F converter but I am not satisfied with the frequency jitter (around 2.5% of the full scale signal), so I tried to mitigate it by addressing the power supply noise. The noise pattern from the analog signal at the sensor matched the power supply noise. The noise pattern includes a 100mv voltage droop based on loading, and a ~100khz 200mv ripple.

Here are some things I tried:

I added a LM7812 regulator with 47uf input cap and 10uf output cap, as well as a 1uf ceramic cap to the sensor power supply. This fixed the measured voltage droop and slightly improved the jitter at the FPGA.

I joined the two grounds at my board. This alone brought the signal jitter down to about 0.5%. I don’t like it though, because it looks like a good way to kill the FPGA due to a ground loop. 24v is supplied to my board via screw terminals; if the + is connected without the ground in place, the capacitors on my board will temporarily raise the negative rail in the FPGA board, which could present negative voltage to the FPGA inputs, which would kill those inputs. Even with a good connector, I cannot guarantee that the ground will be in place before power is supplied. This is why I still plan to use a signal isolator or opto-isolator, along with a 5v regulator for powering the V/F chip.

I still have a 100khz 150mv ripple on my sensor power supply, and a matching ripple at the sensor output. I tried to mitigate it by building a basic capacitor multiplier circuit out of an rc network and an NPN darlington transistor. I must have gotten something wrong because it doesn’t do much to attenuate the ripple. It does appear to be working because there is a several-second startup time where the voltage slowly rises after power is supplied. The values I used are 1K resistor, 10uf capacitor and SD2088 transistor, which has a dc current gain of 2000. Any insights as to why it’s not working? I followed this schematic:

https://www.electronics-notes.com/articles/analogue_circuits/transistor/capacitance-multiplier-circuit.php

I am new to this so I don’t know what I should expect to be able to achieve. I am trying to get the 12v power supply ripple to below 10mv. Is this reasonable?

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    \$\begingroup\$ "which I presume comes from the noise at the analog input." Why do you have to presume when you can check? Hook it up to a scope and see. As for adding the linear regulators everywhere, you never actually told us what you were using the power supply you were using to power the sensor in the first place. You also never told us what amount of jitter you are seeing and what amount of jitter you would be satisfied with. I see little point in using a digital isolator to carry the signal to the FPGA. \$\endgroup\$
    – DKNguyen
    Commented Mar 13, 2022 at 23:37
  • \$\begingroup\$ We just don't have enough info. \$\endgroup\$
    – DKNguyen
    Commented Mar 14, 2022 at 13:13
  • \$\begingroup\$ A cap multiplier is not a filter. RC filters have an R for a reason, not just a capacitance. It likely wouldn't work anyways since it suffers from the same reason why using linear regulators to remove switching noise from an SMPS tends not to work: the circuit has to be faster than the noise to react in time to compensate for the noise, but noise is high frequency (i.e. really fast) so passes right through. You need a series component for a filter to drop noise voltage across. \$\endgroup\$
    – DKNguyen
    Commented Mar 14, 2022 at 14:21
  • \$\begingroup\$ 100kHz is borderline too fast so you can try adding a low resistance or ferrite bead, but the wrong ferrite bead can amplify noise due to resonance/peaking. If that doesn't work, replace the cap multiplier with just a ceramic capacitor (NP0 since other ceramic dieelectrics are piezo and make noise when deformed.) . \$\endgroup\$
    – DKNguyen
    Commented Mar 14, 2022 at 14:24

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Analyze the DC voltage signal in with a Spectrum Analyzer and Oscilloscope and determine what other "noise" is present on the DC. From there, address the undesired signals with filtering.

Voltage regulators are fine, but there are so many places noise is picked up, so a Vreg may not work. Filtering at the input is your best bet.

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