Considering this circuit (NE555 voltage doubler), how can I find the formula for the relation between the value of the load resistor and the output voltage?
You can see below two examples of this circuit, one with 1k ohm load resistor with 8.617V output voltage, and the second with 100 ohm load resistor with 6.233V output voltage.
"I'm mostly interested in how to explain the phenomena" -- JeanMi
That's a big question.
A real circuit isn't ideal. But it's almost always a good thing to first understand ideal circumstances. That way, a feel for what is fundamental about the circuit arrangement can be gathered. And from that vantage, the nonidealities can then be better seen and understood.
This isn't the only way to approach an understanding of all "the phenomena." But it is a good one.
The ideal case is this:
simulate this circuit – Schematic created using CircuitLab
Before startup, \$V_{_\text{OUT}}=V_{_\text{CC}}\$ because ideal diodes \$D_1\$ and \$D_2\$ immediately charge \$C_{_\text{FILTER}}\$.
With that in hand, and assuming \$C_{_\text{DRIVE}}\$ is uncharged, then when the square wave input source starts at \$0\:\text{V}\$ then \$D_2\$ is off and \$D_1\$ is on and the voltage difference across \$C_{_\text{DRIVE}}\$ is immediately just \$V_{_\text{CC}}\$. When the square wave input source next moves to \$V_{_\text{CC}}\$, then \$D_1\$ is off and \$D_2\$ is on and and anode of \$D_2\$ would be at twice \$V_{_\text{CC}}\$ were it not for the presence of \$C_{_\text{FILTER}}\$ to absorb energy and therefore reduce the voltage difference across \$C_{_\text{DRIVE}}\$ to exactly \$V_{_\text{OUT}}- V_{_\text{CC}}\$.
Early, this difference is close to \$0\:\text{V}\$ and all of the energy stored on the drive capacitor is delivered, as the filter capacitor is still charging upwards. But eventually, an equilibrium is reached where the reduced energy delivered by the drive capacitor just matches up with the average energy consumed by the load, each cycle.
There will be ripple, as while \$C_{_\text{DRIVE}}\$ is charging \$C_{_\text{FILTER}}\$ must supply the load current. But we can temporarily ignore this issue by simply assuming that \$C_{_\text{FILTER}}\$ is large enough that we can ignore the question of ripple, for now.
The central point to focus attention towards is this question: How much energy does \$C_{_\text{DRIVE}}\$ deliver when the ideal system is at its equilibrium condition?
When in equilibrium, there are two states to consider:
On the left, the drive capacitor is charged up to \$V_{_\text{CC}}\$ via \$D_1\$ and has a charge of \$\left(V_{_\text{CC}}-0\:\text{V}\right)\cdot C_{_\text{DRIVE}}\$. On the right, the drive capacitor is discharged via \$D_2\$ into the filter capacitor and has a charge of \$\left(V_{_\text{OUT}}-V_{_\text{CC}}\right)\cdot C_{_\text{DRIVE}}\$. The difference between these is the charge that is lifted each cycle:
$$\begin{align*} Q_{_\text{CYCLE}}&=\left[\left(V_{_\text{CC}}-0\:\text{V}\right)-\left(V_{_\text{OUT}}-V_{_\text{CC}}\right)\right]\cdot C_{_\text{DRIVE}} \\\\ &=\left(2\cdot V_{_\text{CC}}-V_{_\text{OUT}}\right)\cdot C_{_\text{DRIVE}} \end{align*}$$
The amount of charge lifted times the lifted voltage height is the energy delivered. In this case, as the charge is lifted from the ground reference up to \$V_{_\text{OUT}}\$, the energy lifted is:
$$\begin{align*} E_{_\text{CYCLE}}&=Q_{_\text{CYCLE}}\cdot\left(V_{_\text{OUT}}-0\:\text{V}\right) \\\\ &=\left(2\cdot V_{_\text{CC}}-V_{_\text{OUT}}\right)\cdot C_{_\text{DRIVE}}\cdot V_{_\text{OUT}} \\\\ &= V_{_\text{OUT}}\cdot\left(2\cdot V_{_\text{CC}}-V_{_\text{OUT}}\right)\cdot C_{_\text{DRIVE}} \end{align*}$$
(That's also the same as \$E_{_\text{CYCLE}}=2 \cdot\left(\frac12 C_{_\text{DRIVE}}\left[V_{_\text{CC}}\right]^2-\frac12 C_{_\text{DRIVE}}\left[V_{_\text{OUT}}-V_{_\text{CC}}\right]^2\right)\$ if you prefer to see it that way.)
We are now at a point where we can make a statement about power. The power is just energy per unit time. And the time per cycle is \$t_{_\text{CYCLE}}=\frac1{f}\$. So the equilibrium power condition is easily stated as \$P=\frac{E_{_\text{CYCLE}}}{t_{_\text{CYCLE}}}=f\cdot E_{_\text{CYCLE}}\$.
Obviously, this must match up with \$\frac{\left[V_{_\text{OUT}}\right]^{2}}{R_{_\text{LOAD}}}\$ in the equilibrium state. So:
$$\begin{align*} f\cdot E_{_\text{CYCLE}}&=\frac{\left[V_{_\text{OUT}}\right]^{2}}{R_{_\text{LOAD}}} \\\\ f\cdot V_{_\text{OUT}}\cdot \left(2\cdot V_{_\text{CC}}-V_{_\text{OUT}}\right)\cdot C_{_\text{DRIVE}}&=\frac{\left[V_{_\text{OUT}}\right]^{2}}{R_{_\text{LOAD}}} \\\\ f\cdot \left(2\cdot V_{_\text{CC}}-V_{_\text{OUT}}\right)\cdot C_{_\text{DRIVE}}&=\frac{V_{_\text{OUT}}}{R_{_\text{LOAD}}} \end{align*}$$
That can be solved for \$V_{_\text{OUT}}\$ as:
$$V_{_\text{OUT}}=2\cdot V_{_\text{CC}}\left[\frac1{1+\frac1{f\,\cdot\, C_{_\text{DRIVE}}\,\cdot\, R_{_\text{LOAD}}}}\right]$$
And here you can now see why it is important that \$f\cdot C_{_\text{DRIVE}}\cdot R_{_\text{LOAD}}\gg 2\$. You want the term, \$\frac1{f\,\cdot\, C_{_\text{DRIVE}}\,\cdot\, R_{_\text{LOAD}}}\$ to be small with respect to 1 if you want the output voltage to approximate a doubling of the source voltage.
You can also solve it for \$C_{_\text{DRIVE}}\$ to get:
$$C_{_\text{DRIVE}}=\frac{1}{f\,\cdot\,R_{_\text{LOAD}}\cdot\left(2\cdot\frac{V_{_\text{CC}}}{V_{_\text{OUT}}} - 1\right)}$$
There's a lot more to deal with, while staying with ideal cases. For example:
A thought to consider here is that \$E_{_\text{CYCLE}}\$ is delivered instantly (ideal case), so the filter capacitor supplies the required current for the entire remainder of the cycle, not just half of it or some other fraction.
The implications of such a consideration should be to expect that the output voltage will look like, in the ideal case but with ripple now included, a sawtooth.
This is then a prediction.
Getting back to the point, the question about the equilibrium behavior of \$V_{_\text{OUT}}\$ can be directly addressed while still keeping ideal diodes and an ideal voltage source for the clocking input. And it introduces another design parameter.
This gets to another prediction that can be made. Since the drive capacitor can be sized only by considering the desired average output voltage, the frequency being used, the supply voltage rail value, and the load, it would seem that the size of the filter capacitor doesn't matter -- except as it applies to the output ripple magnitude. So we should be able to find this result, too.
We now have at least these two predictions beyond where we started, with respect to the equilibrium situation of the ideal case:
I haven't discussed the formula for establishing the size of the filter capacitor. But given #3 above, it is very easy to work out by the simple application of: \$I_{_\text{C}}=C\frac{\text{d}V_{_\text{C}}}{\text{d}t}\$.
If you think there's not more to find in the ideal case in equilibrium and with ripple added, think again. There is a subtle effect due to ripple, once that is injected into one's viewpoint. This is the fact that the drive capacitor cannot completely discharge, as earlier assumed, at the instant of the rising clock edge. This is because the drive capacitor design is based upon the average output voltage. So, if ripple is considered, half of it will be above the average and half below. So on the rising edge most of the charge may be released by the drive capacitor. But not all of what was expected. That will have to slowly "dribble" out as the load gradually pulls down the filter capacitor. (And, in fact, the drive capacitor will continue to supply charge after the average is met because as the load continues to lower the filter capacitor voltage, the drive capacitor will be able to supply still more charge.)
There are always these kinds of refinements to a view. You start simple and work out the details. Then you find, when you look more deeply, there's yet another effect that you'd earlier missed. And so on.
But until you know the larger picture (in this case, that the drive capacitor discharges mostly at the rising edge) and can understand most of the experimental result, you cannot see more deeply into these new effects.
In science, this is a matter of studying residuals. Each time you think you understand something well, you find that you do. But that there still remain some unexplained residuals. So you now focus on those and study them until you gain some insight into one of the causes. You separate out that effect, after more study and thinking about it, and add that knowledge to the prior knowledge to make still better predictions. Then you find there are still more, but smaller now, remaining residuals. And you study those. Etc.
After you have worked out how to size these two capacitors, you can work on nonidealities; such as limitations in the clocking source's current compliance (or impedance) and diode voltage drops and bulk resistance, among others. You might choose to approach these from an energy loss consideration. Or choose a different approach. Up to you.
I hope this approach has achieved two things: (1) Provided some clarity of mind about the ideal situation, from which to begin including nonidealities; and, (2) Illustrated how to deduce theory into specific situations.
In this latter case, it's important to take note of something. I could have blindly applied a quantitative calculation, cross-pollinated from some other circumstance, and used \$\frac12 C V^2\$ directly to the drive capacitor and gotten a wrong answer in doing so. That's because that formula was derived from theory into a different circumstance.
When facing each situation, you need to first decide whether or not the boundary conditions that were used to develop some other formula still apply to the new circumstance. If not, then set the formula aside and re-examine the new case using the same theory as before but now deducing it into the particular circumstance, at hand.
Theory is always right. It's just not quantitative. Theory expresses meaning and relationships. But each circumstance has to be taken into account, when applying theory, in order to develop an appropriate quantitative expression for that particular circumstance.
This is one of the hazards that catches lots of people (including me), unawares. It's all too easy to apply well-worn formulas to new circumstances without taking a moment first to see if they may still apply.
So I want to haul this out in front of you so that it's something you'll remember and keep to heart. General physics theory just works. But it has to be deduced into experimental circumstances in order to generate quantitative prediction for that experimental setup.
Hopefully, this sets things up to allow you to see just a little better and a little further and illustrates an approach towards analyzing the circuit and to develop still further towards a more managed and practical design approach.
Left to you, for now, is to think about how close (or far) from ideal that a practical circuit really is. How much will part variations matter? How sensitive is the circuit to part variations as a function of the selected output voltage (relative to ground) versus the clocking source voltage difference? Does selecting a lower output voltage reduce part variation sensitivity? Or increase it? Etc.
Obviously, part variations can matter a great deal if badly chosen. But the question is more about how much they matter when they are well-chosen. Is there still a wide variation? Or does the design come under enough good management that multiple instances of the same design will provide reasonably predictable results?
With my best wishes...
I thought I'd now finally add some simulations to test the above claims about the equilibrium condition for the ideal case.
A nearly ideal diode can be fabricated for simulation from this Spice card:
.model IDEAL D(Vfwd=1u, Ron=1u)
The forward voltage is only a microvolt and the on-resistance is a microOhm.
I'll also use a .TRAN simulation card that specifies the capture of the simulation only after the equilibrium condition has arrived. I'll use a clocking frequency of \$10\:\text{kHz}\$, so I believe waiting a couple of seconds should be sufficient and that we only need to see about \$10\:\text{ms}\$ worth of data -- about 100 cycles. The .TRAN card I've chosen is this:
.tran 0 2 1.99 1u
I'll also use a \$10\:\text{V}\$ input source voltage supply rail value.
I want to use a clocking source that runs with about 50% duty cycle, so as to highlight and illustrate the effect when the drive capacitor continues to supply a little charge during half the cycle.
I'll run the following cases, first:
You can see the "subtle" effect I mentioned, earlier, where the drive capacitor's charge is mostly disbursed at the rising edge, but not all, and it is allowed to continue supplying charge for half of the cycle (slowly trickling in.) The effect is less noticeable when the ripple is less, of course. But this shows all of the impacts and you can easily see a "kink" in the output voltage with the largest ripple (the red curve) when the clock reaches 50% and moves back to ground.
Now let's lower the output voltage:
In this case, there's much more margin so a much larger percentage of the drive capacitor's charge is disbursed immediately and now the shape of the output voltage with the highest ripple doesn't show much of a kink in it. The top diagram does show the fact that the drive capacitor does continue to trickle charge, as before. But the impact is less noticeable on the output curve, now.
Above, I magnified this subtle effect by choosing a 50% duty cycle. An advantage of doing that is that the formula used to size the drive capacitor was developed on the idea of the average output voltage and so the simulator above does show that this average value is roughly achieved, as predicted. The price of doing that, though, is that the drive capacitor continues to supply charge for a while and a "kink" can be seen in more extreme ripple cases.
I can, on the other hand, remove much of the kink by instead making the duty cycle very small. For example, say 1%, and with a more gentle transition. In this case, the peak voltage is set by the drive capacitor's formula and the filter capacitor formula more accurately predicts the ripple, as well.
I'll show the same two runs as before. But with new clocking that greatly shortens the discharge duration. First the \$19\:\text{V}\$ output case and second will be the \$15\:\text{V}\$ output case:
\$19\:\text{V}\$:
\$15\:\text{V}\$:
Now, the drive capacitor calculation more closely sets the peak voltage instead of the average and the kink is essentially gone, now.
The advantage here now goes to showing that the filter capacitor design equation very accurately predicts the peak-to-peak ripple. (It did so less well, earlier, because of the fact that the drive capacitor continued to supply charge for half the cycle.)
Between these two pairings of runs (total of four charts), one can see that both the drive capacitor and filter capacitor equations, developed from idealized assumptions, do work well at making predictions -- within the limits of the assumptions used to derive them from theory (such as instant discharge at the rising edge.)
We could further improve (complicate) them by taking into account the fact that charge continues to be provided during the period between the rising and falling clock edge, for example. But that's for another day. At least we know we could do it, if we wanted, and how to approach that refinement should it be needed.
What if you made two of these and arranged them this way:
This is just a half-Dickson and it will increase the voltage by another step. So it triples the voltage (about), instead of doubling it. I did this by using the output of the first state as the "\$V_{_\text{CC}}\$" for the second stage. Nothing more than that.
You can continue this idea over and over again.
And a full-Dickson would drive the filter capacitors, as well:
Or you can re-arrange the diodes and get a negative voltage rail this way:
All I did was flip the diodes over and instead of \$V_{_\text{CC}}\$ supplying \$D_1\$'s anode, I'm now using ground to supply \$D_1\$'s cathode.
There is an entire family of related ideas here. Be sure to visit the Wikipedia page on voltage multipliers.
how can I find the formula for the relation between the value of the load resistor and the output voltage ?
The formula is quite complex because it involves not only the charge and discharge curves of the coupling capacitor but also the high and low output voltage drops in the 555 at various currents, which are significant.
I reproduced your 1 kΩ load circuit with real components, and measured voltages with a multimeter and oscilloscope. I used SS34 Schottky diodes for low forward voltage drop (~0.2 V each). The 33 μF capacitor dropped 0.3 V due to ESR and 0.7 V overall (charge/discharge curve + ESR).
Depending on which brand of '555' IC I used the output voltage ranged from 6.26 V for an HA7555 to 7.54 V for an LM555. The minimum voltage drop at pin 3 when high was consistently 1.4 V on all 9 of the samples that I tested. Minimum voltage drop when low varied from 0.1 V for the LM555 to 1.2 V for the HA17555.
With a 100 Ω load the output voltage collapsed to below 5 V. The Falstad simulator is not at all accurate at this loading.
Falstad's simulated 555's output is going up close to 5 V, not the expected value of 3.6 V. Just in case it uses a CMOS 555 model I tested a TLC555 and a 7555 with 1 kΩ load. The TLC555 put out 6.85 V, and the 7555 put out less than 5 V. These results are expected because although the CMOS version has full 5 V output swing its maximum output current is lower than the bipolar 555. So the Falstad model is not a good representation of either the bipolar or CMOS 555.
I also simulated your circuit using LTspice with a 555 model called "μA555 transistor level 555 timer model" designed for greater accuracy than the standard model. It calculated the output voltage at 6.49 V, with waveforms similar to what I saw on the oscilloscope. This voltage is close to the actual voltage I measured with a real μA555, which was 6.43 V.
Takeawys from this experiment are:-
Manual calculations can be useful, but in complex circuits they are often tedious and error-prone. A simulator can provide more accurate results faster, provided the models used are appropriate.
Don't expect great accuracy from a simulator using 'generic' component models, particularly in circuits where some characteristics may be critical.
Don't trust a simulation using complex components without checking that they match datasheet parameters, and verify the performance in a real circuit before committing to a design.
With a 1 k load your circuit is working close to the limit and may have quite different output voltages depending on the particular '555' chip used. Dedicated 'voltage doubler' ICs are available which do a much better job.
This answer might not be what you had in mind, but it's an extremely useful concept/technique in electronics which can be used in many applications. Your circuit is nonlinear and complex with switching waveforms, so it's difficult to derive an analytic formula or use manual calculations. However, by only changing the load resistor and keeping everything else constant (supply voltage, diodes, caps, duty cycle), you already have two data points:
(1000Ω, 8.617V)
(100Ω, 6.233V)
You can draw a straight line using these two points, which means you can get a linear approximation to the circuit under your desired conditions & output (in your case, the voltage across the load resistor after the capacitor stabilizes). Depending on several factors such as the underlying circuit properties/topology, the distance between the two sample points, or how far away you're approximating a solution away from those two initial points can all affect the resulting approximation. Generally, if you keep the points fairly close together or don't stray too far away from them, you can get pretty good results for a decent amount of circuits.
Moving forward, if we can assume linear operation we can apply Thévenin's theorem and redraw the entire circuit to the left of the load resistor as a Thévenin equivalent:
where we can calculate \$V_{th}\$ and \$R_{th}\$ using your two data points of (1000Ω, 8.617V) and (100Ω, 6.233V). Will this approximation end up working out reasonably well? Let's try it and see. If we add in the load resistor, the circuit looks like this:
which is the classic voltage divider circuit and is described by the following formula:
$$ V_{out} = V_{th} \cdot \frac{R_L}{R_{th} + R_L} $$
If we plug in your two data points which are in the form \$(R_L,V_{out})\$ into two separate instances of that equation we are left with two equations and two unknowns (\$R_{th}\$ and \$V_{th}\$). Doing the algebra (which I won't delve into) results in the following values:
$$ \begin{align*} R_{th} &\approx 44.4 \Omega \\ V_{th} &\approx 9.0 \text{V} \end{align*} $$
For completeness, here are generalized equations for \$R_{th}\$ and \$V_{th}\$ which can be used for the same equivalent circuit with two measured data points. Simply plug in the values from \$(R_{L1},V_{out1})\$ and \$(R_{L2},V_{out2})\$ into the first equation. Then use this result along with one of the data points (doesn't matter which one) in the 2nd equation to find \$V_{th}\$.
$$ \begin{align*} R_{th} &= \frac{R_{L1}R_{L2}(V_{out2} - V_{out1})}{V_{out1}R_{L2} - V_{out2}R_{L1}} \\~\\ V_{th} &= V_{outx} \cdot \frac{R_{th} + R_{Lx}}{R_{Lx}} \quad \text{for} \ x = 1 \ \text{or} \ 2 \end{align*} $$
I will add our Thévenin equivalent circuit to your Falstad simulation and compare the results when using the same load resistor between the actual circuit and the equivalent one. Let's first verify if our calculations are correct by seeing if we get the same output voltage for the same initial two load resistors, i.e. if our linear approximation indeed passes through the same data points.
Okay, that's pretty dead-on. Now let's see what we get for 550Ω, which is the mid-point of the original two points:
8.332V vs 8.328V, which is pretty darn close. How about 50Ω (half of 100Ω)?:
4.759V vs 4.768V......hey, I'll take it. One last one. Let's do 2kΩ (double of 1kΩ):
8.810V vs 8.805V. Okay, you get the point. So what this all means is you can approximate the output voltage vs load resistor using the following voltage divider equation:
$$ V_{out} \approx 9.0 \text{V} \cdot \frac{R_L}{44.4 \Omega + R_L} $$
Where does this approximation break down? Probably somewhere, but I'll leave that as an exercise for anyone reading. The point is that it works reasonable well under this circuit and all our assumptions for a decent range of load resistances. This concept is quite useful for analyzing unknown circuits such as the output of an IC pin. Characterizing the output as a Thévenin equivalent can help you successfully interface such unknown circuits with your external analog circuitry. Simply take a couple bench measurements when the circuit is operating near your desired range, and plug those data points into the generalized equations to get \$R_{th}\$ and \$V_{th}\$.
APPENDIX: I'll paste in the code for the Falstad circuit below, in case someone doesn't want to recreate the circuit from scratch (like I had to do).
$ 1 0.000005 382.76258214399064 49 5 50 5e-11
165 224 208 256 208 6 0
r 144 144 144 304 0 1000000
c 144 336 144 400 0 1.0000000000000001e-7 0.001 0.001
r 240 112 336 112 0 10000
g 144 400 144 432 0 0
g 320 400 320 432 0 0
w 320 400 320 368 0
w 224 336 144 336 0
w 192 304 192 112 0
w 384 272 384 112 0
w 240 112 192 112 0
v 480 160 480 208 0 0 40 5 0 0 0.5
R 144 144 80 144 0 0 40 5 0 0 0.5
w 144 144 288 144 0
w 288 144 288 176 0
207 384 272 384 320 4 out
c 384 272 480 272 0 0.000032999999999999996 0.001 0.001
g 480 160 480 128 0 0
d 480 208 480 272 2 default
d 480 272 544 272 2 default
c 544 272 544 352 0 0.001 0.001 0.001
w 352 240 352 144 0
r 608 272 608 352 0 1000
g 544 352 544 384 0 0
w 608 272 544 272 0
w 192 304 144 304 0
w 224 304 192 304 0
w 144 336 144 304 0
w 608 352 544 352 0
x 502 193 527 196 4 14 \p5V
v 384 448 384 384 0 0 40 9 0 0 0.5
g 384 448 384 464 0 0
r 464 384 464 448 0 1000
r 384 384 464 384 0 44.38
w 464 448 384 448 0
w 352 144 288 144 0
w 336 112 384 112 0
w 352 272 384 272 0
207 608 272 656 272 4 Actual
207 464 384 496 384 4 Equiv
x 403 423 428 426 4 14 \p9V
o 38 64 0 4098 10 0.00009765625 0 2 38 3
o 39 64 0 4098 10 0.00009765625 1 2 39 3
This voltage-doubler is not very good with a low frequency and very large output cap.
But the output impedance is dependant on dV/Ic=dt/C and your RC timer T= 10k 100nF= 1ms with about 70% * 1/T = 700Hz and Zc= 1/ 2pifC= 1/ (6.28 * 700Hz * 1e-7) = 2k2 ohms with 3rd harmonic = Zc/3. Thus even 1k will drop the voltage > 10%.
So if you want decent load regulation at 100 Ohms then the cap must be <5% of Zc(f) or 5 Ohms. Then make both caps the same !
