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I want want to connect a clock to a pin. And I want to use a *.xdc-file for this.. But finally Vivado tells me :

[Synth 8-3331] design clocktester has unconnected port sysclk2

its not really unconnected.. but iam scarred,

[Synth 8-3330] design clocktester has an empty top module

is it really that empty?

[Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.

Is this important?

My design will be like this and i am confused because even here, at this simple code comes those errors. The testbench should simulate the sysclk2 from outside.

*.xdc set_property PACKAGE_PIN A7 [ get_ports sysclk2 ]

create_clock -period 12.3 [get_ports sysclk2]

design vhd:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clocktester is
  Port ( 
      sysclk2 : in std_logic      
  );
end clocktester;

architecture Behavioral of clocktester is

signal clk1 :std_logic;
signal clk2 :std_logic;
begin
clk2 <=sysclk2;

    p_test : process(sysclk2)
    variable t : natural := 0;    
    begin
    t := t+1;
    end process p_test; 

end Behavioral;

also using a simple testbench

entity tb is
--  Port ( );
end tb;

architecture Behavioral of tb is
component clocktester 
port (
     
      sysclk2 : in std_logic

);
end component;
  signal sysclk2: std_logic;
  
  
begin

dut : clocktester

port map (
  sysclk2 => sysclk2 

);
            
p_clk_gen : process 
begin
wait for 3.2 ns;


sysclk2 <= '1';
wait for 3.2 ns;
sysclk2 <= '0';
end process p_clk_gen;          

end Behavioral;
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1 Answer 1

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Your design has one input but no outputs. The synthesizer has decided that there is no reason to actually create your design in the FPGA hardware because it has no effect on anything in the FPGA. So, the synthesizer has just discarded everything in your design. Since the design is discarded, there is no longer a connection to sysclk2.

If what you really want to do is simulate the design, then don't try to synthesize it.

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  • \$\begingroup\$ omg ok thank you! I will add an output and check it again^^ \$\endgroup\$
    – t1fpga1
    Mar 16, 2022 at 6:15

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