Can I drive a low-voltage MOSFET gate directly from a microcontroller?

Question

We're working on this project for school where "reducing the number of components is essential".

We need to operate a little brushed DC motor so we thought of using a simple low-side drive configuration with an N-channel MOSFET like this one here: IRLHS6242PBF

How do I know if a microcontroller's GPIO has enough "power" to drive that MOSFET? Here is the link to the microcontroller we're thinking of using.

I looked at the gate charge of the MOSFET in the datasheet, the rise time of our PWM signal and the maximum GPIO current of 25 mA and from my calculations it looks like the controller should be able to drive the MOSFET gate without a problem as long as the required PWM rise time allows it. Am I actually wrong? How would you calculate it?

EDIT: We're aiming at a switching frequency of 1 kHz, not much more than that, I think.

Answer 1

The answer is yes, and no. I mean it depends on what you need to do with the load.

For simple and relatively slow on/off switching you can do it provided that…

Your MCU has sufficient output level: most logic level mosfets are characterized for a Vgs of 4.5V; usually in the cover page you see the manufacturer boasting their Rds at 10V (standard level) and 4.5V (logic level)

Your MOSFET is a so-called super logic level, it's characterized at 2.5V in this case; there are even 1.8V gate level MOSFETs (usually for low power environments).

Note that you pasted the absolute values for the GPIO ports: these are not quite as interesting as the typical values, for this purpose. On your datasheet table 17 has the answers.

Be sure that your maximum VOL is below your gate threshold (to avoid erroneous starts!). You have 0.4 max on the MCU and 0.5 min on the MOSFET, so it's OK. Also remember a gate pulldown to ensure the MOSFET stays off when the port is tristated (during reset, usually).

For the ON condition you need to check the VOH. Your target is at least 2.5V (the output curve on the MOSFET datasheet tells the whole story). So you need at least 3V of supply on the MCU.

Notice the condition column in the table: the specified values are stated at 8mA. CMOS output cells are somewhat nonlinear (i.e. they don't have exactly an output impedance). The idea is that you ask for more current the port will not reach the stated performance.

For the current the issue is slightly more complicated: as you probably know the gate terminal is substantially a capacitor (the other terminal is the source, of course). Turning on/off the MOSFET is simply charging/discharging that capacitor (almost: it's a composite capacitor that has different charging phases).

As a first approximation you need to look at Ciss (the input capacitance of the MOSFET). That's about 1.1nF in this case. Another useful parameter is the total gate charge Qg (it tells how much you need to charge the gate)

So, to recap:

• You have about 2.5-2.8V of GPIO available;
• You need to charge a 1.1nF gate capacitor;
• You have at your disposal about 8mA of current;
• When you have put about 18nC of charge in the gate the MOSFET has completed the switching (well, it finishes before but it's simplified).

To limit the GPIO current of course you use a resistor. Remember that an empty capacitor is almost a short circuit so you need to limit the whole 2.5-2.8V output to 8mA. Ohm's law helps.

This is everything you need for a simple, slow, MOSFET switch (remember to freewheel the motor inductive demagnetization, obviously). In this situation the MOSFET is (substantially) fully enhanced and dissipates as an Rdson resistor.

Now, for PWM you have two main issues:

• With only 8mA the switching operation is slow. Really. You can use the RC circuit exponential behaviour to determine the switching time, in theory. In practice these days you usually use a simulator (often SPICE based) to know how much time it takes; this limits the frequency you can use for you PWM (remember that you also need to discharge the gate for turning the MOSFET off, so the minimum period is twice the time!)

• During the commutation the operation point moves thru the linear region, so the Rdson value is not valid anymore. In this region Vds is significant and power dissipation can be a concern (these are called switching losses). Of course the more time it take more joules are wasted in heat.

Losses depend on the current needed for your motor but can be estimated. You can't do a thing for static (Rdson) losses. Switching losses can be reduced charging faster the gate, i.e. with more current. Then you need a gate driver and there are more issues. You can use gate drivers even at logic level (if the driver works at such a low voltage).

A good introductory appnote is SLUP169 Fundamentals of MOSFET and IGBT Gate Driver Circuits from TI.

Answer 2

The easiest way to get some numbers here would be to simulate the transistor. Barring that, there's some back-of-the-envelope calculations you can get to figure out what's going on. Note that I used the values from the datasheet excerpts, not the actual linked datasheet (they're different).

Approximate the MOSFET gate charge (Qg) as an ideal capacitor. Note that this gate charge is dependent on VDS and IDS, and the datasheet is picking an arbitrary value. Also note that the gate capacitance is non-linear, so really is an approximation, not a solution. $$C=Q/V = 3.1 nC / 4.5 V = 689 pF$$

Assume a resistor in series to limit current to GPIO limit: $$R_G = VDD_{IO}/I_{MAX} =3.3V/25mA=132\Omega$$ Increase the resistor to the next available resistor size, e.g. 150Ω.

Approximate the rise/fall time as a RC time constant. The switching behavior is not well modeled by this assumption, this is just to get a rough order of magnitude estimate. Using 2.2 time constants gives roughly a 10%-90% transition and is a bit pessimistic. This also assumes that the GPIO drive strength is equally good across all output voltages. $$T_{sw} \approx2.2 RC\approx3*150\Omega *689pF = 227ns$$

So that's not super fast, but it's not terrible. Actual output switching time will probably be less. I'd probably look into it further for lower PWM frequencies.

Answer 3

GPIO outputs are well approximated by current sources driving a current somewhat smaller than the short-circuit current the GPIO pin can drive into either rail. Usually the GPIO drivers have the same current source and sink capability. The gate is well approximated by a capacitor connected to the source. It'll be easy to determine the slew rate, and thus gate voltage (a ramp), and the moment when the mosfet will start to conduct, and when it will be fully turned on.

In general, single MCU outputs don't have enough current capacity to turn low resistance mosfets on and off quickly enough to minimize the switching losses. If you can afford to have many more GPIO pins available than nominally needed, it's a decent strategy to parallel multiple pins to increase the effective current. This requires adding power pins to the MCU. That's done by having "dummy" GPIO outputs connected to GND and VCC, and driving them to 0/1 logic state, respectively. Those outputs provide additional parallel supply paths for the adjacent drivers that drive the mosfet gate. The parallel power path pins would be alternated with output pins that drive the gate, to keep I/O power ring currents down.

This trick can be used to provide much higher combined GPIO currents than would otherwise be achievable, without overstressing the chip even if the absolute maximum total pin current is exceeded.

This is only feasible if particular attention is paid to characterizing such operation and ensuring that the I/O power ring won't be damaged by such currents. Such shenanigans make sense in high volume low cost products, where shifting as much responsibility onto the MCU as possible saves cost in spite of higher R&D expense. For low-volume products, just use a gate driver if you're in any doubt. It will be much cheaper.

Answer 4

Look at Figure 1 in the datasheet for the MOSFET. This figure tells you the typical value of \$V_{DS}\$ for a given value of \$V_{GS}\$ and \$I_D\$. Use only the curve that corresponds to the \$V_{OH}\$ for your processor.

Verify that the MOSFET can supply enough current for your load, while maintaining a sufficiently low \$V_{DS}\$.

If you want to estimate how fast the microcontroller can switch the MOSFET gate, use the typical total gate capacitance for the MOSFET and the minimum \$I_{OL}\$ and \$I_{OH}\$ for your microcontroller. Given average current and capacitance you can calculate an estimated \$\frac{dV}{dt}\$. If you know how much you want the voltage on the MOSFET gate to change (\$dV\$, usually equal to the microcontroller supply voltage) then you can calculate an estimated \$dt\$.

The parameters you included, \$V_{GPIO\_ABS}\,\$ and \$I_{GPIO\_ABS}\,\$ are absolute maximum ratings for the device and package; these parameters are not relevant here.

Answer 5

Taking a very rough estimate from the datasheet, the worst case(fastest) turn on time is around 20ns and the gate charge required is 0.22nC. So the Ig comes around 10mA which is lesser than your sourcing current of the uController.

Answer 6

Here is a simple example with 100W 12V motor using the Falstad default model.

• I used an Nch FET with Vt=1.5V, Vgs=12V PWM variable f & d.c.and a default (10A est?) power diode

Note that the plots show power generated by the Voltage source is negative about 95 W steady state and also for DIODE and FET (~ 20 mohm)

Ps=95W, Pfet=1.5W, Pdiode=7.3W

Can I drive a low-voltage MOSFET gate directly from a microcontroller?

Yes... but's there's a lot more design questions to designing a motor driver.

How do I know if a microcontroller's GPIO has enough "power" to drive that MOSFET?

The GPIO doesn't provide power to the motor but the outputs do have low resistance \$R_{oh}=(V_{dd}-V_{oh}/I_{oh} \$ is usually < 50 Ohms @ 25'C depending on Vdd. (rated GPIO current is for logic levels @ Vol and Voh which are less relevant here so use the computed RdsOn)

Important Facts about GPIO SPECS

• Do not use the Absolute Max current to design your drivers, you should not be coming close to these limits. -Instead compute the current and ensure it operates BELOW ABS LIMITS

• Compute Rout like this

  \$V_{OH}= \dfrac{V_{DD} – 0.5V}{8~ mA} = \dfrac{3.3-0.5}{8}=350 ~\Omega (abs.max @ 85°C)\$

FET's use gate capacitance charge (see Ciss) voltage and the Vgs(th) (aka. Vt) gate threshold is for a high resistance. To achieve low RdsOn about Vgs>=2 * Vgs(th) is required and RdsOn is rated near this.

Gate rise time can be estimated from Ro * Ciss. Output slew rate depends on load reactance RdsOn and Coss. ref I suggest you get a half-bridge FET or full-bridge ( for bi-directional) power motor driver IC until you get familiar with all the design parameters.

https://www.pcbway.com/blog/technology/Powerful_H_Bridge_DC_Motor_Driver.html

Layout is critical to good performance with ground plane for low inductance and good decoupling.

Normally a push-pull driver aka Half-Bridge is better as the single PWM switch with a diode clamp acts poor-man's push-pull ( Nch pull + diode push switch to Vdd from back EMF). However these are prone to shoot-thru failure unless you design with fast-off, slow ON to create a defined "dead-time or break-before switching rails. This is a normal design.

Give me feedback on simulation.