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circuit

In the above circuit, why does the propagation time Tp > Th? As I understand it, once the first D-FF changes value, it will propagate that value to its output, that is the Tp. Then on the input side of a D-FF we have the Th which is the amount of time needed for the input to be stable after a clock edge (why must it be stable for that time after a clock edge???). What I don't understand is why the above stated relationship must hold?

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  • \$\begingroup\$ OK, I think I understand where it comes from. It would be right if Tp is referring to some logic between the registers - which is not shown here. In that case, after the clock is changing, the input to the second register needs to be stable for at least Th. And the propagation delay of that logic will ensure that. \$\endgroup\$
    – Eugene Sh.
    Mar 15, 2022 at 17:02
  • \$\begingroup\$ @EugeneSh. Sure, now we're back to my original question. I don't get this. Feel free to post a detailed answer if you will. \$\endgroup\$
    – NoName123
    Mar 15, 2022 at 17:05
  • \$\begingroup\$ So let's assume Tp is referring to the propagation delay from CLK to Q0. It means that after the clock is changing, Q0 will remain stable for at least Tp. Th is referring to the minimum time the signal needs to be stable in the input of the second register. So if Tp > Th, then it is satisfied. Otherwise it isn't \$\endgroup\$
    – Eugene Sh.
    Mar 15, 2022 at 17:11
  • \$\begingroup\$ @EugeneSh. Ok I believe your answer makes sense. If Tp was to be less than Th then Q0 could potentially end up unstable and as such when the second FF samples a new value, it'll potentially enter into a metastable state. Is that correct? \$\endgroup\$
    – NoName123
    Mar 15, 2022 at 17:17
  • \$\begingroup\$ Yes, sounds correct \$\endgroup\$
    – Eugene Sh.
    Mar 15, 2022 at 17:20

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