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I'm testing an AES encryption machine that's written in Verilog. I know that the DUT is perfect because I created a Verilog testbench.

When I simulate in VCS, the clk stays at 0 the whole time and the rest of the input/outputs are X. In the log file, none of the transactions are printed so I think that it's a clock problem.

I'm getting a warning for ANSI redeclaration for the clk, so I commented out the clk wire in the interface but the result is the same.

Am I missing a connection? Or am I not connecting the DUT correctly? Do you always have to use clocking blocks and modports with a modular testbench in SystemVerilog?

`timescale 1ns / 1ps

//Top Level
module top();

  //clk generator
  reg clk = 0;
  always #5 clk = ~clk;
   
  
  //DUT Instantiation
  aes_intf intf(clk);
  
  aes_128 DUT(
    clk,
    intf.key,
    intf.state,
    intf.out
  );
  
  testcase test(intf);
  
endmodule


//Connections to DUT
interface aes_intf(input clk);
  //wire clk;
  wire [127:0] state, key;
  wire [127:0] out;
endinterface

//Instances of driver, etc
class environment;
  driver drvr;
  virtual aes_intf intf;
  
  function new(virtual aes_intf intf);
    this.intf = intf;
    drvr = new(intf);
  endfunction
  
endclass
//Stimulus Generator for 128-bit AES Encryption DUT
`timescale 1ns / 1ps

//Base Transaction
class transaction;
    rand bit [127:0] state;
    rand bit [127:0] key;
                          
    function void print(string tag="");   //print for log file
      $display("state=0x%h  key=0x%h", state, key);
    endfunction
  
endclass

//Generates stimulus and drives to DUT
class driver; 
  rand transaction trans; //transaction object
  int iterations;
  virtual aes_intf intf; //interface instance
  
  //Constructor
  function new(virtual aes_intf intf);
    this.intf = intf;
  endfunction
  
  task drive(input integer interations);
    repeat(iterations) begin    //send x transactions
        trans = new();
      @(posedge intf.clk);
      if(!trans.randomize())$fatal("Transaction failed");
        intf.key = trans.key;
        intf.state = trans.state;
    end
  endtask

endclass
`timescale 1ns / 1ps

program testcase(aes_intf intf);
  
  environment env = new(intf);
  
  initial begin
    env.drvr.drive(10);
  end
  
endprogram
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1 Answer 1

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You have a typo in the driver class (interations). Change:

  task drive(input integer interations);

to:

  task drive(input integer iterations);

You did not get a compile error because you declared iterations as a class-level variable.

The problem with your simulation was that no time elapsed in the drive task. When you passed the value 10 to drive, the interations variable was assigned to 10. However, the iterations variable remained 0 because you declared it as int, and you did not assign it a value. Therefore, the repeat loop never executed, and the simulation ended at time 0.

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