We're doing a course on Computer Architecture, and the course project involves creating an ARM-based processor.

We're supposed to create the processor in stages, and add significant features in each stage. So far, progress has been good: I've been able to create the major modules and make them work in a datapath and add a FSM-Based controller, all in VHDL of course.

However, with each passing iteration, the datapath becomes more and more complicated to cater to the different types and formats of ARM instructions.

The current datapath I have is littered with more multiplexers and word extenders than major processor components themselves, and adding any new feature is similar to taking a walk in a swamp. Even textbooks like Patterson and Hennessey use the same approach while designing processor datapaths:


I could not find any actual microarchitecture descriptions online, because they're all private IP. Most datapaths I did find simply abstract away the complexity involved in transferring data in the form of 'buses', as such:

nehalem microarch

This led me to my question:

  • How is processor datapath design done in industry. How are complicated datapaths implemented to cater to even more complicated instruction sets without designers adding an infinitude of multiplexers?
  • 5
    \$\begingroup\$ "without adding an infinitude of multiplexers": Modern CPUs have hundreds of millions of standard cells. Why would "I have a lot of multiplexers in this design" be anything bad? Why would it even be remarkable? A CPU is something that does things depending on other things, i.e. something that basically screams for multiplexers! \$\endgroup\$ Mar 16, 2022 at 19:12
  • 2
    \$\begingroup\$ I believe this question is too advanced for this site. \$\endgroup\$
    – Miss Mulan
    Mar 16, 2022 at 19:28
  • 5
    \$\begingroup\$ @MissMulan I'll have to strongly disagree here - we have some true experts in their fields here. A full design of a datapath at transistor level would be too much for an answer, but an overview of the design of a datapath, common tradeoffs, etc is perfectly plausible and we have plenty of high-level answers on such "advanced" topics. In fact, the comment given just above by Marcus can very well be the start/foundation of such an answer. As an analog designer trying to branch into digital, I'm eagerly hoping to see a full answer here soon. \$\endgroup\$
    – nanofarad
    Mar 16, 2022 at 19:43
  • \$\begingroup\$ Part of it is that you can conceptually simplify the multiplexers. Where you have several cascaded as in the top right, to form an N:1 mux, simply use an N input OR gate per bit of the bus (so 8,16,32 OR gates). Then AND each input with a control signal, and guarantee elsewhere that only one input's control signal is '1' at any one time. Now at least it's easy to see how few gates are really involved and how cheap they are.(If you can get the AND (or "zero the output when not wanted") for free from the preceding functionality, you can save gates in ways that would be harder with a multiplexer. \$\endgroup\$
    – user16324
    Mar 16, 2022 at 22:31

3 Answers 3


without designers adding an infinitude of multiplexers?

You typically won't be implementing such a design literally according to the design schematic, by laying out logic blocks/cells like in the 70s, or using discrete digital logic chips.

In modern days, the multiplexers are means for humans to express their intent. The logic synthesis software will translate those into a variety of physical implementations that perform the same logic function, but are faster, consume less power, take less space on the die, etc. For example, you could design an adder circuit with multiplexers, and good tools will translate it into a much better adder design, and will use adder cells if such are available in the target library (be it for an ASIC or in an FPGA).

As for whether a multiplexer best expresses your intent? That's for you to decide first, for human coworkers second, and for industry practices (also all stemming from human factors) last.

Just how complex is a real CPU datapath?

More complex than entire CPUs and their chipsets from 2-3 decades ago. In other words: as long as it fits on the die, has good enough yield, and performs adequately, the other measures of "complexity" become largely irrelevant, for complexity is subservient to the function. If the function can be practically achieved but takes "extreme" complexity of the datapath: so be it, after all it works, sells, and makes money. In my eyes, that's success aplenty!


The components of the datapath are standard (as indicated in the picture of the question): arithmetic logic unit, which includes adders, multipliers, and shifters, for integer and floating/fixed -point arithmetic; registers (specifically flip flops) to enable pipelining; decoders; and memory subsystem(s).

That said, for each major (sub-)component, such as adders, multipliers, and even decoders, there exists multiple circuit designs to implement that (sub-)component. However, there selection is based on design objectives and constraints.

More generally, the datapath is co-designed with the control path of the processor architecture or microarchitecture. The design of the processor architecture is based on techniques in computer architecture (e.g., superscalar, out-of-order, highly-pipelined) and VLSI system design (e.g., using the method of logical effort to minimize the delay/latency of the logic/digital circuit, skew-tolerant domino logic, asynchronous digital IC design, synchronous elastic systems, dynamic/adaptive voltage and frequency scaling or DVFS, clock gating, and power gating) to optimize the VLSI implementation.

More recently, a revisit to the previous topic of design-technology co-optimization (DTCO) that concurrently optimizes the VLSI implementation of the processor architecture concurrently with semiconductor manufacturing technology (3-D ICs, wafer-scale IC implementation or wafer-scale computing, and chiplet-based VLSI/SoC design) and semiconductor device engineering (new devices, such as different memristor designs). This affects the architecture and datapath of the processor design.

    Address = {Long Grove, {IL}},
    Author = {John Paul Shen and Mikko H. Lipasti},
    Publisher = {Waveland Press},
    Title = {Modern Processor Design: Fundamentals of Superscalar Processors},
    Year = {2013}}

You can make a multiplexer from simple logic gates with the appropriate Karnaugh Map so the control circuit can look like the internal circuit of a multiplexer but not be exactly the same with the modifications made for some type of the processor.


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