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When looking up datasheets on logic gates, propagation delay is usually shown as a range. Sometimes there's a "typical" value in the middle, but there's a min and max listed. On what does the range vary?

Take this chip for example: https://www.ti.com/lit/ds/symlink/sn74auc2gu04.pdf?ts=1647469241013 enter image description here

At 1.2 volts, the propagation delay is shown as MIN 0.7ns and MAX 3.1ns. Is it just basically random each time? Does it depend on temperature? High->low vs low->high?

I don't really know how to handle that range, and it's likely to matter for my application.

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    \$\begingroup\$ Especially for a 20 year old IC like that the delay may change over the years as manufacturing changes, etc. Think of the spec as giving them a range of values they have to stay within for as long as they sell the product, not necessarily a range of values any particular batch of parts will necessarily cover. \$\endgroup\$
    – user1850479
    Mar 17, 2022 at 0:17
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    \$\begingroup\$ Multiple separate things: how does it vary a) over that family of parts (i.e. manufacturing variation, tolerance) and b) for that specific part (due to voltage and temperature). And c) how does it vary for that specific part, over time (ageing) \$\endgroup\$
    – smci
    Mar 19, 2022 at 2:19

3 Answers 3

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The propagation delay can vary with manufacturing conditions as well as operating conditions. Temperature probably will play an effect. However, the point is, you can't control the propagation delay. You are only guaranteed (assuming the honest manufacturers) that the propagation delay will be within the limits specified if the chip is operated under the limits specified. You are not guaranteed anything more.

I don't really know how to handle that range, and it's likely to matter for my application.

If this is a one-off, diy project, then you can try your circuit, and if it works to your satisfaction, then great. If it does not, you can try another chip, or tweak some component values.

However, if you plan to make multiple circuits, or if you need guaranteed reliability, then I strongly recommend that you redesign your circuit so that propagation delays (within the specified limits) will not affect the correct operation of the circuit. Even if the circuit works correctly with one batch of chips, it may fail with another batch of chips. Or it might work in someone's cool basement, but fail when placed in a hot attic. Or any other of a variety of situations. Except for single dyi projects that you don't mind tweaking, always design so that the circuit will work correctly even if the components happen to be at the limits of their specified tolerances.

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  • \$\begingroup\$ Are you even guaranteed anything for sure? Is it impossible that very rarely the propagation delay will fall outside the stipulated interval even when under optimal operating conditions? I had the impression that logic gates might (rarely) fall into a metastable state, and stipulated operating conditions merely reduce that risk to a very small (but still nonzero) likelihood. \$\endgroup\$
    – user21820
    Mar 17, 2022 at 9:10
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    \$\begingroup\$ @user21820: Metastability is really only a thing in flip flops when you have a timing violation on the input. Which kind of means you are operating outside of specification and there are no guarantees on the output level/voltage. \$\endgroup\$
    – Michael
    Mar 17, 2022 at 12:31
  • \$\begingroup\$ @user21820: The propagation time minimum is specified from the time the inputs leave a valid state, and the propagation time maximum is measured from the time the inputs re-enter a valid state. In some cases, valid input conditions depend upon a device's current state, and an input condition which would have been valid before a partial transition may cease to be valid. For example, suppose a Schmitt trigger input is specified to register a change from low to high somewhere between 3 and 4 bolts, and from high to low somewhere between 1 and 2 volts. If the input goes from 0.5V (valid low) \$\endgroup\$
    – supercat
    Mar 17, 2022 at 14:54
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    \$\begingroup\$ you are not guaranteed anything no. There is going to be a failure rate of so many parts per thousand or million just do to mfg process if nothing else. You validate the design, and you build wafers that intentionally lean fast and slow, and you exercise the parts from those wafers. You also have experience from that process, company ABC and DEF may have run millions of parts before XYZ came along and decided to make parts at that foundry with that process. So some of it is design, some is experience, some is testing. And some parts slip through \$\endgroup\$
    – old_timer
    Mar 20, 2022 at 0:45
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    \$\begingroup\$ You do not test every part to destruction nor test the to the point of damage. You need to get each part/wafer through the fixture fast, so you do what you can and expect that there will be some that fall through. Based on failure analysis of the ones that fall through that you can analyze, you may or may not choose to add more tests, not add more tests, add an errata, change the documentation, or just do nothing... \$\endgroup\$
    – old_timer
    Mar 20, 2022 at 0:47
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Is it just basically random each time?

No - from microsecond to microsecond it will be fairly stable. Over longer periods it will drift, especially with temperature.

Does it depend on temperature?

Yes, very much so. Most digital logic is a temperature sensor whether you want it to be or not.

High->low vs low->high?

Some of the better data sheets quote them separately. They are not guaranteed to be the same, although they will move together.

I don't really know how to handle that range, and it's likely to matter for my application.

You haven't told us what the application is, but generally you have to "design it out" so that the variance in delay doesn't matter.

While the different devices in a package won't have exactly the same delay, it will be very close, and they will tend to move together because they're all the same temperature inside the package. Does that make your life easier?

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Most logic gates use CMOS technology and the MOSFETs inside the logic gate have Source-Gate capacitance.That is why there is a delay.

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