Intel FPGA Avalon I2C (Master) Core IP: Where are SCL_OUT and SDA_OUT?

Question

This is for Intel MAX10 (10M08) FPGA, NIOS 2 soft core, Quartus (free version), windows 10.

I'm trying to understand this ip core because I need to connect external tri-state buffer to it. The thing that baffles me the most is that I don't see a clock (scl) and data (sda) out signals. The picture below is what the block for the core looks like in the platform designer. The top picture is without clicking the box to "show signals". I click the "show signals" box in the lower picture. I see the sda_in (serial data in), scl_in (serial clock in), sda_oe (serial data output enable) and scl_oe (serial clock output enable). A tri-state buffer (to me) should have 3 pins: in, out and enable. The "Embedded Peripherals IP User Guide" shows (bottom picture) the input for the buffers as "1'b0" and the verilog code for scl shows "assign arduino_adc_scl = i2c_serial_scl_oe ? 1'b0 : 1'bz;". This verilog code to me says that depending on the output enable signal the buffer output is either 0 or hi-z. So where is the data and clock out? Thanks

Answer 1

I2C is an open drain bus with a pull-up resistor.

The IO pin is either set low or let float by a device. It is not allowed to be set high.

So as per the schematics, the state of the IO pin can be always read as input signal, and the state of IO pin can be set low with the output enable signal when necessary.