My understanding of the DDR4 calibration process is that DQS is derived from a common clock with a PLL, then passed through a DLL to apply deskew such that DQS and CK edges arrive in sync.

Is there some standard (e.g. JEDEC-defined) limit to the amount of skew correction that can be applied to DQS during link training on a DDR4 memory controller? If there's no standard limit, is there a general ballpark timing correction range that DDR4 memory controller implementations typically allow for?

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    \$\begingroup\$ DDR4 is a JEDEC-standard, so you'd want to look there first. I bet you the figure you're looking for is within the standard. \$\endgroup\$ Mar 17, 2022 at 21:10
  • \$\begingroup\$ @Kubahasn'tforgottenMonica I had a quick look before but couldn't find it in there, but a more thorough dig through it revealed the terminology I was looking for: "Write Levelling". I'll self-answer with the info. \$\endgroup\$
    – Polynomial
    Mar 17, 2022 at 22:06

1 Answer 1


A more thorough dig through the JEDEC DDR4 SDRAM spec revealed what I was looking for. The link training for correcting skew between DQS and CK is implemented in a feature called Write Levelling. The timing details for this are on pages 195 to 196 of the spec. The timing range for the write levelling output delay (tWLO) is specified as 0ns to 9.5ns for DDR4-2400. Timings for the other speeds are marked TBD in the copy of the spec I was able to find.

Beyond the spec, this article was very helpful in describing the procedure in further detail.

I was not able to find any information on typical tWLO values in practical implementations. 9.5ns seems like a very long delay considering typical DQS cycle times, so I would expect it to be far lower than that in practice.


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