My understanding of the DDR4 calibration process is that DQS is derived from a common clock with a PLL, then passed through a DLL to apply deskew such that DQS and CK edges arrive in sync.
Is there some standard (e.g. JEDEC-defined) limit to the amount of skew correction that can be applied to DQS during link training on a DDR4 memory controller? If there's no standard limit, is there a general ballpark timing correction range that DDR4 memory controller implementations typically allow for?