# Trying to understand Integral nonlinearity in DAC/ADC

So here's the definition of INL:

it is mentioned (underlined in red) that one of the lines can be a line drawn between the end points of the transfer function but in (a) that line appears to pass in the center of the perfect transfer function and not in the end points, am i missing something?

Same thing happens here:

in this case the INL is defined as the deviation of the mid-points of the quantization steps between the ideal and real transfer function, where the ideal transfer function is exactly situated in the mid points of the perfect transfer function (not the end points).

In the first image there's also this:

"The name integral nonlinearity derives from the fact that the summation of the differential nonlinearities from the bottom up to a particular step, determines the value of the integral nonlinearity at that step."

How so? If i add the previous 2 errors in the last image i provided here i will get the next error?

Also in these 2 images :

Why is the Vlsb measured equal to the difference between two digital voltages divided by 2n -2 in ADC, why not just 2n?

Why is INL only defined for 2n - 1 points for ADC and 2n points for DAC and DNL only defined for 2n -2 for ADC and 2n -1 for DAC?

And last question is related with the picture below:

Why does the ADC only have 2n -1 voltages?

• 2^N-1 steps between 2^N voltages Commented Mar 18, 2022 at 0:04
• Can you link where you got this erroneous info? Commented Mar 18, 2022 at 0:13
• What image are you talking about? They are all from different sources Commented Mar 18, 2022 at 0:14
• the last image has text in error Commented Mar 18, 2022 at 0:17
• The last image was taken from a power point done by my professor. There's no source, i think it's done by him. What's wrong with it? Commented Mar 18, 2022 at 0:18

It is important to consider how DNL and INL are measured for DAC and ADC devices.

For a DAC, each point in the transfer function is determined by measuring the analog output level at each DAC code. There are $$\2^N\$$ codes and $$\2^N\$$ resulting analog output levels.

Since INL is defined by the difference between measured and ideal outputs for each code, it is defined for $$\2^N\$$ points, between code $$\0\$$ and code $$\(2^N-1)\$$.

DNL is determined by the difference in the measured outputs for two adjacent codes (denoted as codes $$\n\$$ and $$\n+1\$$ in the equations in the question). The last defined DNL point is determined by the difference between codes $$\(2^N-2)\$$ and $$\(2^N-1)\$$, since $$\(2^N-1)\$$ is the last defined code. We can see that, at the full scale of the DAC, $$\n\$$ corresponds to code $$\(2^N-2)\$$ (and $$\n+1\$$ corresponds to $$\(2^N-1)\$$). Thus, DNL is defined when $$\n\$$ is in the range of $$\0\$$ and $$\(2^N-2)\$$.

For an ADC, measurements are made by observing the locations of the transition points between codes. An ADC with $$\2^N\$$ codes has $$\(2^N-1)\$$ transition points.

Note: Transitions can be located by observing when the digital output is toggling between two adjacent codes. This can be accomplished by using a variable analog input source (often controlled by a servo loop) and determining the transition points. (Transitions may also be located statistically using a histogram test, but that is outside the scope of this answer).

For an ADC, the INL is defined by the difference between the measured transition point and the ideal transition point for each transition. Since there are $$\(2^N-1)\$$ transitions, we have $$\(2^N-1)\$$ defined INL values, in the range of $$\0\$$ and $$\(2^N-2)\$$.

The DNL is determined by the measured difference between two adjacent transitions and the ideal difference between those two transitions. Because there are $$\(2^N-1)\$$ transitions (numbered $$\0\$$ to $$\(2^N-2)\$$), the last defined DNL point is based on the difference between transitions $$\(2^N-3)\$$ and $$\(2^N-2)\$$. So, in this case, $$\n\$$ corresponds to transition $$\(2^N−3)\$$ and $$\n+1\$$ corresponds to $$\(2^N−2)\$$). Thus, DNL is defined when $$\n\$$ is in the range of $$\0\$$ and $$\(2^N-3)\$$.

ADC 's and DAC's both have a full range of values = $$\2^N\$$

But there are two ways to define INL error.

The most common is a deviation from the ideal line from end-end values

Yet Calibration tests always 1st measure Gain & Offset error. So it is possible to reduce INL errors by offsetting the graph.

But more common are missing codes due to ground noise on the Vreg with design errors with noise. This is when digital values of SAR shift Vref to miss a code during xx111111 to xx100000 type logic noise transitions.