0
\$\begingroup\$

I have returned to my 150W inverter simulation and have a new problem I can't decipher. This is the design:
Push Pull Schematic

It runs, it allegedly has good efficiency, and it creates a stable 180V output voltage. I've included a leakage inductance of 198nH on each primary winding to simulate stored energy in the transformer windings. I'm getting ringing on the drains which I expect, and I've added an RC snubber to reduce them. However, at the point of turn-off for the mosfets there is an enormous drain voltage spike up to 100V. It might be higher, but the Vds breakdown is 100V and I suspect the spike is even higher but the models are simply clamping it there.
FET drain voltage spike

I have experimented with diodes across drain-source, freewheeling diodes across drain-Vin, but the former does nothing and the latter severely distorts the switching waveform. When I check the primary input waveform of the transformer after the leakage it does not have these spikes:
Transformer primary post leakage

I'm not sure how else to dissipate this stored leakage energy without interfering with operation. Since it happens at turn-off I wonder if there is a better drive scheme I can be doing? The whole idea of simulation was to identify issues that could destroy components but I'm not sure how to reduce this spike. Any help is appreciated.

\$\endgroup\$
3
  • \$\begingroup\$ the Rdson is 23 mΩ and the R/L=T values matter ! 1 uOhm? dead-time is important \$\endgroup\$ Mar 19 at 1:38
  • \$\begingroup\$ What is the pulse voltage across the snubber resistor, R1. Is it constant with the magnetizing current at turn-off? There would also be some self-capacitance of the transformer that would reduce the pulse. The avalanche energy rating for the MOSFET is probably large enough so no damage would result in real-life. There is a diode, D1, not connected to anything. Unconnected components sometimes mess up SPICE. \$\endgroup\$ Mar 19 at 1:45
  • \$\begingroup\$ Why do you have 2 trafos? What coupling do they have? Why the 1u resistors, they can't be realistic. And why waste a full bridge when you could have had only two diodes? Also, do yourself, and others, a favour and use the already existent symbols for diode and MOSFET, it'll make for a much clearer schematic. As you probably know, if they're subcircuits instead of models, you need to change the prefix to X, in rest it works just like a .model. \$\endgroup\$ Mar 19 at 7:34

3 Answers 3

1
\$\begingroup\$

While a snubber might work, it is not very precise and therefore needs to be overdesigned.

The general way to do this is to control (reduce) the strength of the gate drive. This can be difficult because there is a tradeoff with dead time control and with gate lift-up.

A zener diode across the D-S of each FET will work, but it needs to handle the peak current. Alternatively a zener (+ series diode) from D-G will allow the FET to handle the current. You might need to increase the 10 Ω gate R to keep the zener currents within reason.

\$\endgroup\$
0
\$\begingroup\$

One idea is to make the primary resonant by adding a capacitor between the drains. Another is to add a 50V transient voltage suppressor between the drains.

\$\endgroup\$
0
\$\begingroup\$

First RC snub the output diodes this will waste power .Aim up your parts for low Q damping the resonance .Then turn off snub the mosfets wasting more power .Next do some energy recovery to get most of the power back .

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.