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For a project/learning experience I want to design/build an amplifier.

The signal I’m provided has an approximately 1ns pulse width (duty cycle of 1%) with a peak of 2.2V and a repetition frequencyof 100ns, 10MHz. This signal comes directly from a 74LVC2G08 dual AND gate (both 1Y and 2Y are connected together.) I’m not sure about the output impedance of the gate, checking with an oscilloscope (appropriate bandwidth) I’m getting 2.2V and 40mA. The signal from the AND Gate should drive a load (only resistive) of 50 ohm at 5V (100mA).

DC voltage sources are available with 12V and 5V (if needed I can provide 16V or more, but no more than 16V would be preferred.)

I’m not sure how to design a circuit with BJT NPN transistors to get the needed 5V at the 50 ohms load.

Some research led me to find the following forum thread, where the author „electroman“ mentions the following:

There's no need for 10 GHz Ft transistors, a good design can use humble BSX20's etc...

You only need a tiny gain of 100 and a single emitter coupled pair will give that without problem. The speed of the edges will be around the 200 pSecond region depending on layout etc... To drive 50 ohms you will then need a simple emitter follower with a pull down as output, operating in class A mode will be sufficient.

I would like to implement the following advice into my needed amplifier, but I’m not sure it makes sense in my case and I don't know how to design the emitter follower/ differential amplifier and emitter follower. For the BJT I would use the CMPT2369 since this is the SMD alternative tp the BSX20. (Additionally I have the following NPN transistors available: BFG590, BFR106, NSVF6003SB6.) A simulation of a differential amplifier with the 2N2369 gave me an output peak of approximately 5V on OUT2.

Differential Amplifier Test

Can someone with experience help me design the amplifier to get the needed signal?

Summary of the restraints/conditions:

  • 1ns pulse width signal provided by a 74LVC2G08 dual AND gate at a repetition rate of 10MHz, 2.2V peak and 40mA
  • Voltage supply available 12V/(16V) and 5V
  • NPN transistors available: BFG590, BFR106, NSVF6003SB6 or if possible 2N2369
  • Amplifier needed to drive 50Ohms load with 5V and 100mA

Datasheets of the mentioned NPN transistors:

Other datasheets (if needed):

Update 23/03/2022 to the questions asked from @aconcernedcitizen @TonyStewartEE75 @jonk @Barry @Antonio51:

  • Yes, I do intend in the future to use a different logic gate group (like CML/ECL)
  • Output does not need to be a perfect replica of the input (if it is even better), only thing needed is short (~1ns) pulses into the resistor. Gain should be around 2 at the output, and only single ended input available.
  • AND Gate is powered by a 5V source (not a 2.2V rail as supply rail) - I do think due to the fast switching the 5V is attenuated to the ~2.2V peak.
  • I do get a 1ns pulse (see attached oscilloscope image). The oscilloscope had an bandwidth of 3GHz. scope 1ns
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    \$\begingroup\$ Somebody will know better, I'll just say that, if you want to use SPICE to test the schematic then you shouldn't just rely on the models/subcircuits as they are. First, and foremost, test them to see that they match the datasheet curves as close as possible. (Too) many models are simply not even fit to be considered as equivalents. Also, for those timings you'll need to add in device/PCB parasitics (this is not an "if", it's a "must"). \$\endgroup\$ Mar 19, 2022 at 20:26
  • \$\begingroup\$ In order to prevent reflections you will need matched impedances throughout. That means no load must be 10V and 5V with load. dI/dt will be severely distorted with ringing unless well designed. recheck your design specs and list them to be sure. But you might be able to get away with mismatched sources ganged together < 22 ohms and lose only 25% with load matched with path delay << risetime. You may get better results with CML. \$\endgroup\$ Mar 19, 2022 at 20:32
  • \$\begingroup\$ You may also want a differential CML for better performance \$\endgroup\$ Mar 19, 2022 at 20:41
  • \$\begingroup\$ ulix, what are you trying to achieve? Does the output need to be a good replica of the input? If so, there are a number of "effects" to be concerned about (output conductance change, emitter current change, etc.) Is the signal bipolar or unipolar? Are you talking only of a voltage gain that is approximately 2? Or do you just want to replicate the signal with gain=1 (seems like 'no' here, but I'm asking) but into 50 Ohms? Single-ended or differential input? Maybe I'm just not reading well, today. \$\endgroup\$
    – jonk
    Mar 19, 2022 at 21:06
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    \$\begingroup\$ Are you really getting a 1 ns pulse out of the NAND gate? The specs on that gate imply rise and fall times of about 2 ns each. What is the bandwidth of your scope; it needs to be several GHz in order to reliably display such short pulses. \$\endgroup\$
    – Barry
    Mar 19, 2022 at 22:22

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