We are using the FPGA ProASIC3E A3PE1500-PQ208. The FPGA got internally short circuited during runtime. The FPGA IO Supply Voltage and FPGA ground are permanently short circuited and it is not reprogrammable after the short circuit as TDO does not toggle.
The most recent code had dynamic switching between the IOs which caused the FPGA device to go out of normal operation mode (This point is mentioned in the FPGA fabric guide). The coding practice till now was not to internally tie up/down the unassigned IOs. Looking at the FPGA fabric details document, the inference was that unused IOs are either given high impedance or weakly pulled up. Now, if several IOs are weakly pulled up to 3.3V it is dangerous and induces a fault in our case.
What is the protocol to avoid such internal IO short circuit faults in PQ208 devices?