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I am having trouble understanding where manufacturers are coming up with their length matching requirements. For example, I am looking at length matching for RGMII between a MAC and PHY.

My understanding is that, at gigabit speeds, the interface runs at 125MHz and double data rate. This gives a bit time of 1 / (2 * 125,000,000) = 4 ns.

Now, a very rough approximation for the propagation speed in the PCB is c/sqrt(epsilon_r) so let's just call it 6 mil/ps for this example (dielectric constant of around 4.0).

So, given a very generous specification for setup and hold times of 1 ns, this should still give 1ns of allowed skew between the clock and data lines. This equates to 1000ps * 6mil/ps = 6 inches of allowable length mismatch.

However, the largest allowable length mismatch I have seen given by a manufacturer is 400 mils. That is over a magnitude difference between my calculate allowable mismatch and what the manufacturer is recommending.

Clearly I am missing something here, but I have not been able to figure out what it is. Any clarification or insights would be greatly appreciated!

Thanks,

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The rise time is what extends the BW and importance of impedance matching and skew time. This will be about 10% to 20% of the clock period which explains your over-estimate. \$f_{-3dB} = 0.35/T_R\$ using 10%~90%.

Clock to data skew is +/- 500 ps max.

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  • \$\begingroup\$ Hi Tony! Thanks for the reply. Sounds like I am not properly taking into account the rise time of the signal. I am trying to understand the rest of your response. So you are saying that you can estimate the bandwidth of the signal from the rise time using the given formula? How does that bandwidth then inform your length matching requirement? Thanks! \$\endgroup\$ Mar 21, 2022 at 23:42
  • \$\begingroup\$ You imagine that upper -3 dB frequency is what you want to limit in your latency skew Here is your calculation with rise time limit and unequal delays. tinyurl.com/y97abcys remember if the latency is less than the rise time, the echos/ringing/skew will be diminished. if the rise time is too fast, then matching is more critical to prevent ringing \$\endgroup\$ Mar 22, 2022 at 0:11
  • \$\begingroup\$ I apologize, but I still do not understand how the signal bandwidth translates to a length matching requirement in this case. Does it help if I clarify that I am specifically talking about groups of single-ended signals? Because I know that for differential pairs the rise time has a much greater impact on the length matching requirements in order to avoid common mode currents. I am not sure what the simulation you linked is trying to show. It seems useful in explaining for differential signals but not as much for single ended. \$\endgroup\$ Mar 22, 2022 at 0:20
  • \$\begingroup\$ here with 5x the allowed 10 mm limit with 0 rise time to show max jitter tinyurl.com/yd2ud2xz to demonstrate skew between combined data . clock data skew must be 500 ps \$\endgroup\$ Mar 22, 2022 at 0:23
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    \$\begingroup\$ Not quite. there exists a budget for every source of jitter from source mismatch, load mismatch rise time differences and delay differences and CMRR all affect SNR & BER, so there is an allocation budget for each \$\endgroup\$ Mar 22, 2022 at 1:12

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