# Trouble understanding length matching requirements

I am having trouble understanding where manufacturers are coming up with their length matching requirements. For example, I am looking at length matching for RGMII between a MAC and PHY.

My understanding is that, at gigabit speeds, the interface runs at 125MHz and double data rate. This gives a bit time of 1 / (2 * 125,000,000) = 4 ns.

Now, a very rough approximation for the propagation speed in the PCB is c/sqrt(epsilon_r) so let's just call it 6 mil/ps for this example (dielectric constant of around 4.0).

So, given a very generous specification for setup and hold times of 1 ns, this should still give 1ns of allowed skew between the clock and data lines. This equates to 1000ps * 6mil/ps = 6 inches of allowable length mismatch.

However, the largest allowable length mismatch I have seen given by a manufacturer is 400 mils. That is over a magnitude difference between my calculate allowable mismatch and what the manufacturer is recommending.

Clearly I am missing something here, but I have not been able to figure out what it is. Any clarification or insights would be greatly appreciated!

Thanks,

The rise time is what extends the BW and importance of impedance matching and skew time. This will be about 10% to 20% of the clock period which explains your over-estimate. $$\f_{-3dB} = 0.35/T_R\$$ using 10%~90%.