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I've been taking an CS Engineering Course where I've chosen minors in Electrical engineering. I'm a total noob here and no idea what's basically going in chip/FPGA Design process.

I wished to ask if there is any way to convert Verilog program to Digital Logic Gate design? (I suppose that's how it happens and it's called Verilog to Digital Logic Synthesis)

So, apart from manually drawing digital logic gates in the sheet of paper, is there any way I can use some sort of program to get Digital Logic design and if possible simulate it too?

I looked up for programs, but Intel FPGA Tools/Xilinix ISE Professional suit seems out of scope to install in lab computers (~5.5/20G + installation time too), Also, I'd give my preference to open source tools over closed source ones.

Here, I wish to avoid paper as much as possible. So, is there something I can get my help with? or how others actually do?


In terms if my question seems similar/duplicate to - Open Source verilog synthesizer I'd like to clarify if any other approach to synthesis exists if no programs are open source. The goal here is open source approach to FPGA.


Edit - I found the closest tool - https://github.com/itsFrank/MinecraftHDL but for some reason, it won't help much + no simulation support here...

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  • \$\begingroup\$ "CS Engineering Course where I've chosen minors in Electrical engineering" may be known by another name: Computer Engineering or CE. And yes, you can take some Verilog and translate it into logic and FF state. Called "synthesis." Have you tried? For any given FPGA, there is also "floor planning." That can be manual or automated. (It is worth some time playing with it, manually.) You can use entirely open-source and free tools. That's a cool thing. But I'll let my betters tell you how. \$\endgroup\$
    – jonk
    Mar 22, 2022 at 6:28
  • \$\begingroup\$ Interesting question. What do you think are the differences between your question and the duplicate you highlighted? It might help to point them out if you don’t want your question to be closed as duplicate. \$\endgroup\$ Mar 22, 2022 at 6:47
  • \$\begingroup\$ @NickBolton I guess the question which I've highlighted as similar but not same one is about Open Source Tools for Verilog-Logic Synthesis. Clearly, there aren't any such open source tools as highlighted by accepted answer (the other tools aren't much helpful either), so, I'm here seeking for manual alternative techniques for such cases where FOSS tools aren't available. 🙏 \$\endgroup\$ Mar 22, 2022 at 8:38
  • \$\begingroup\$ @jonk I suppose Floor Planning comes after logic synthesis and simulation state (please correct me If I'm wrong 🙏). Please suggest any FOSS Floor planning tool if you know, that'd be helpful. \$\endgroup\$ Mar 22, 2022 at 8:39
  • \$\begingroup\$ It looks like you are complaining about the size and installation time of a possible solution. Why don't you try it and come back if you have a specific problem? \$\endgroup\$ Mar 22, 2022 at 10:34

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The question you linked to is from 2013; about 9 years old today. Currently, there is at least one solution for easily access to free high-quality tools which are oriented toward learning. The site https://www.edaplayground.com/ provides free versions of 4 commercial simulation tools (including Modelsim-now called Questa) and 3 synthesis tools. They run in the cloud, nothing to install nothing to download, no license to have. They want your email to register then just use them. Start in 1 minute. For simulation there is a window to enter your testbench on the left and another window to enter your RTL code on the right, and a big run button. There are limitations; for a beginner or student you should not run into much of a limitation. The nature of the limitation is they want the site to be for learning and not for professional use.

The site https://verificationguide.com/verilog-examples/
has example code that runs on edaplayground with one click (no setup). There is a library of free example code there that runs on a free full-featured simulator. There are other sites that provide example code that runs on edaplayround with one click.

The edaplayground site itself contains examples that run with one click.

Jonas (Author of vhdlwhiz.com) has this list of simulators and related information you may find helpful https://vhdlwhiz.com/free-vhdl-simulator-alternatives/
He mentions edaplayground.

Your asked about creating a gate level design using synthesis. This idea of 'gate level' synthesis output is an abstraction. Generally, synthesis output is a netlist which contains primitives for a particular ASIC or FPGA library, which in may or may not contain gates depending on the libraries targeted. The library consists of primitives defined by the vendor which correspond to a physical FPGA or ASIC resources. When targeting a Xilinx FPGA some examples would be a LUT or CLB or slice. In many cases the synthesis output is intended for machine processing not for human reading, it probably would not do you much good in terms of understanding it. The closest helpful tool output is the schematic view that some synthesis tools provide which show registers, logic blocks and primitives like clock buffers and RAMs. The schematic view is very helpful in terms of understanding how the synthesis tool interpreted your design. Xilinx Vivado can easily provide a schematic view of the post-synthesis design.

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A free open source synthesis tool is available from open circuit design, it is called Qflow. It can be downloaded in ubuntu via apt, note that ubuntu can be run with Oracle's virtualbox. You might also want to google open source vlsi design tools for further sources of useful tools.

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  • \$\begingroup\$ It appears that Qflow synthesizes to a standard cell design; that is not what the OP asked for. They specifically stated that their target is an FPGA. \$\endgroup\$ Oct 18, 2022 at 13:24

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