I've been taking an CS Engineering Course where I've chosen minors in Electrical engineering. I'm a total noob here and no idea what's basically going in chip/FPGA Design process.
I wished to ask if there is any way to convert Verilog program to Digital Logic Gate design? (I suppose that's how it happens and it's called Verilog to Digital Logic Synthesis)
So, apart from manually drawing digital logic gates in the sheet of paper, is there any way I can use some sort of program to get Digital Logic design and if possible simulate it too?
I looked up for programs, but Intel FPGA Tools/Xilinix ISE Professional suit seems out of scope to install in lab computers (~5.5/20G + installation time too), Also, I'd give my preference to open source tools over closed source ones.
Here, I wish to avoid paper as much as possible. So, is there something I can get my help with? or how others actually do?
In terms if my question seems similar/duplicate to - Open Source verilog synthesizer I'd like to clarify if any other approach to synthesis exists if no programs are open source. The goal here is open source approach to FPGA.
Edit - I found the closest tool - https://github.com/itsFrank/MinecraftHDL but for some reason, it won't help much + no simulation support here...