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I have a four-layer PCB that contains a circuit that measures voltage from a very high impedance node. This voltage is a DC voltage value ranges from 33 V to 36 V.

The voltage measurement circuitry is present in the top layer. I have provided guarding only on top layer since all my components are SMT.

My board contains only analog circuitry. Below is my stack up. The stack-up is SIG-GND-Power-Signal. The PCB material is ISOLA Tg 180.

Will the leakage current flow from the other layers to layer 1?

From my stack, you can see that the dielectric thickness is on the order of 4.3307 mil which is 0.1 mm.

The volume resistivity for the 185HR material is 300 tera-ohm·cm. Since our dielectric thickness is 0.1 mm, the volume resistivity will come to 0.3 tera-ohm·cm.

With a VBIAS voltage of 36 V, we can expect the leakage to be 36 V/0.3 tera-ohm·cm. The leakage will be on the order of 120 pA. This can be a problem to us.

enter image description here

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  • \$\begingroup\$ I don't really understand this question. It seems like you've answered it yourself or what is the actual question? If your calculations are correct? \$\endgroup\$
    – Klas-Kenny
    Mar 22 at 7:03
  • \$\begingroup\$ The calculation is definetely not correct. To calculate the resistance/leakage current you also need to take the area into consideration. \$R = \rho d / A\$ \$\endgroup\$ Mar 22 at 7:07
  • \$\begingroup\$ @Lars,if you don't mind could you please help me to calculate \$\endgroup\$
    – HARI T O
    Mar 22 at 7:19
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    \$\begingroup\$ Yes. leakage will occur. No, leakage won't occur at the 120 pA level, that just sounds plain wrong by a few orders of magnitude. Contamination effects will dominate leakage in practice. If really low level leakage is a problem, then air is a much better dielectric than plastic, string the sensitive nodes up in the air in a rat's nest type construction. \$\endgroup\$
    – Neil_UK
    Mar 22 at 7:32
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    \$\begingroup\$ I recommend that as well as calculation, you build something. At this level of leakage, you'll find things you didn't expect. I recommend reading some of Bob Pease's stuff, analogue guru who worked for Nat Semi, especially this on building a femtoamp-level test system for CMOS amplifier input leakage. \$\endgroup\$
    – Neil_UK
    Mar 22 at 8:52

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The distance \$d\$ between your two layers is 0.1mm. The resistivity \$\rho\$ you provided is 300 TOhm cm. To calculate the resistance you still need to know the area \$A\$ of overlap between your high impedance node on top layer and your GND layer: $$R = \frac{\rho d}{A}$$ Since I don't know the area, this is an example assuming \$A = 1 \mathrm{cm}^2\$: $$R = \frac{\rho d}{A} = \frac{300\;\mathrm{TOhm}\;\mathrm{cm}\cdot 0.01\; \mathrm{cm}}{1\; \mathrm{cm}^2} = 3\; \mathrm{TOhm}$$ If you sensitive high impedance node is smaller, the resistance can obviously be significantly larger.

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  • \$\begingroup\$ Thank you .My board size is 30cm*20cm \$\endgroup\$
    – HARI T O
    Mar 22 at 7:38
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    \$\begingroup\$ But the copper area of the sensitive node you are measuring is probably a lot smaller than your board. \$\endgroup\$ Mar 22 at 7:44
  • \$\begingroup\$ ,You are correct the area is very small \$\endgroup\$
    – HARI T O
    Mar 22 at 8:09

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