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I was testing the AD712 on LTSpice with a simple voltage follower.

enter image description here

In a perfect world, I'd get this.

enter image description here

Instead, I'm getting this.

enter image description here

Now, I am aware that op-amps do not reach their V+ and V- voltage and usually fall a bit before that limit. However, according to the AD712 Datasheet (p.4) the output characteristics for V+ and V- = +-15V should be +13.9 and -13.3 respectively, a reduction of 1.1 and 1.7 volts. While for my use case of V+ and V- = +15V and 0V, I am getting reductions of 2 and 3 volts.

enter image description here

Is there something in the datasheet that I missed? Or perhaps, some method of circumventing this issue?

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  • \$\begingroup\$ If you can't design in some supply voltage headroom relative to the inputs and outputs, you should look for a rail-to-rail input and output amplifier. \$\endgroup\$
    – swineone
    Commented Mar 24, 2022 at 12:08

1 Answer 1

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Is there something in the datasheet that I missed?

The input voltage range (but the device is fully characterized for +- 15V only):

enter image description here

And this note is also important:

Typically exceeding −14.1 V negative common-mode voltage on either input results in an output phase reversal.

So, you can't power it with +15V and 0V and input a signal which reaches these two values.

Within the limits it looks fine:

enter image description here

enter image description here

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