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I'm trying to understand the reason why USB and PCIe (considering a single lane) can achieve higher data rates than e.g. SPI, I2C, UART.

The reason may be the better handling of signal impairments at PHY level, so it can work at higher clock rates.

Furthermore, sometimes USB and PCIe are referred as analog serial interfaces, referring how the actual physical transmission takes place. From interface perspective all these interfaces are digital, while the analog refers to the actual inter-chip transmission. Why SPI is somehow not clustered as an analog transmission as USB or PCIe are? Context where I get this classification (digital vs analog): I work in mobile platforms and experts in inter-IC communication tend to refer to the low-speed serial interfaces as digital and USB/PCIe as analog, as said, it looks like that they refer to the needs for a PHY which covers the aspects highlighted by some of the below replies (signal conditioning, differential transmission, ...)

Could you please share your understanding?

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    \$\begingroup\$ Furthermore, sometimes USB and PCIe are referred as analog serial interfaces - please cite a reference. \$\endgroup\$
    – Andy aka
    Mar 25, 2022 at 12:51
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    \$\begingroup\$ @TypeIA UART, or any other protocol can have a differential PHY. That's why RS485, RS422, LVDS or CAN etc exist. \$\endgroup\$
    – Justme
    Mar 25, 2022 at 13:51
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    \$\begingroup\$ SPI can be implemented with a single shift register. PCIe and USB hide much more complexity in the PHY (SerDes, clock recovery, 8b/10b (or higher) encoding/decoding and more) \$\endgroup\$
    – Lior Bilia
    Mar 25, 2022 at 14:25
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    \$\begingroup\$ @TypeIA Sure. Just use any differential PHY like RS485 or LVDS and you get long range SPI, TI has an appnote on that. And there's PCA9615 for long range differential I2C comms. But UART itself has no concept of a standard PHY so UART itself is single-ended. \$\endgroup\$
    – Justme
    Mar 25, 2022 at 14:41
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    \$\begingroup\$ @winny, Just one clarification the comment regarding "analog" interface, referred how the signal is transmitted from PHY perspective, not the user interface which is always digital for the interfaces here discussed. \$\endgroup\$
    – Hadamard
    Mar 26, 2022 at 10:27

2 Answers 2

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There's a number of improvements that need to be made to get from the MHz of SPI/I2C to the GHz of PCIe/SATA/HDMI.

The low speed interfaces assume full-swing logic level signals. When the speed becomes too high for the medium to maintain a good pulse shape, they give up. The high speed signals are small swing and assumed to be degraded by the transmission medium, and both transmitter and receiver take steps to mitigate this (pre-emphasis and equalisation respectively).

The low speed interfaces are single-ended, the high speed ones differential. At high speeds, you can't rely on a well controlled ground at the far end, you need to look at the difference in voltage between two signal lines.

The low speed interfaces have the clock generated from just one end. In read mode, that requires an out and back round trip of the transmission distance, severely limiting the data rate. The high speed interfaces are source synchronous, clock and data (sometimes) or data with clock/timing embedded in it (more common) are sent from whichever node is transmitting.

Some interfaces make use of some of these improvements, but it really takes all of them to increase speeds significantly. UART for instance uses timing embedded in the data.

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  • \$\begingroup\$ Thank you for sharing your view, it goes in line to the above comments and my initial interpretation. \$\endgroup\$
    – Hadamard
    Mar 25, 2022 at 15:38
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All interfaces do "require" a PHY. This is nearly a matter of definition. To move from low-level microscopic-size internal digital domain to a heavy-loaded long wires/board traces always require some sort of a DIFFERENT set of transistors inside a IC. In simple protocols they are usually called "driver". Just some interfaces have more complex circuitry for the transition to PHYSICAL domain.

In simple cases the "driver" could be just a circuit that matches the impedance of attached traces (transmission lines), again with a different level of complexity. This is already a challenging task, and most IC pads already use hundreds of integrated transistors.

In cases of USB/PCIe etc., the digital data are arranged in packets. Before entering physical world, these packets are wrapped with extra transitions like sync preambles, extra bits to balance the bitstream, form special "end of packets", etc. Finally the PHY makes enhancements to signal edges so it can look less distorted when arriving at far-placed receiver. On the receiving end the PHY usually makes compensation for non-uniform signal deterioration, does CDR - clock-data-recovery etc. More, the receivers (and transceivers, like in USB4) undergo "link training" on every individual connection. All these operations do the same routine for every data packet, so it is natural to offload these functions to a separate IP block, called PHY. All these enhancements allow much higher data rates as compared to the simple bit toggling as in I2C or SPI.

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  • \$\begingroup\$ thank you for the comprehensive reply \$\endgroup\$
    – Hadamard
    Mar 28, 2022 at 11:08

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