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Just starting with FPGAs and stuck with a synthesis issue.

Basically, the circuit I am designing is coming out with 0 logic units and 0 for all resources except for the pins assignment. The code compiles (with a few warnings) and it seems fine, but when it comes to fitting/placement, nothing shows up.

The circuit is purely combination, asynchronous and has no clock.

I've tried some example simple circuits such as flipflops and they work fine.

So anyone know why/scenarios/cases where FPGA synthesis on Quartus gives 0 LEs ?

Thanks.

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Without the code, you can only expect general advice.

However the most likely scenario is that the outputs don't actually depend on the inputs, so that optimisation eliminates all the logic in between them and hardwires the outputs to '1', '0' or 'Z'.

This can often be due to a mistake in your logic, or a reflection of the fact that you are trying out an incomplete design, and the missing portions contain logic that would prevent the optimisation from deleting what you have done so far.

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  • \$\begingroup\$ Hmm yeah this seems likely... Will update with findings... \$\endgroup\$ – nehz Mar 18 '13 at 14:59
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you check the warnings when you are compiling your code. Mostly synthesis issuses can be solved if you correct those warnings.

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