Just starting with FPGAs and stuck with a synthesis issue.
Basically, the circuit I am designing is coming out with 0 logic units and 0 for all resources except for the pins assignment. The code compiles (with a few warnings) and it seems fine, but when it comes to fitting/placement, nothing shows up.
The circuit is purely combination, asynchronous and has no clock.
I've tried some example simple circuits such as flipflops and they work fine.
So anyone know why/scenarios/cases where FPGA synthesis on Quartus gives 0 LEs ?