I have the decoupling capacitors located close to sparatan 7 (<2000 mil). I'm trying to route these and connect it to the BGA pin. According to xilinx UG393, I shouldn't use same vias.
PCB layout engineers often try to squeeze more parts into a small area by sharing vias among multiple capacitors. This technique should not be used under any circumstances. PDS improvement is very small when a second capacitor is connected to an existing capacitor’s vias. The capacitor mounting (lands, traces, and vias) typically contributes about the same amount or more inductance than the capacitor's own parasitic self-inductance.
I'm trying to connect them using single trace and then add a via to touch the 3.3 V power plane. I don't think this will induce any additional parasitic capacitance. I'm placing a via perpendicular with short trace. Is this correct ? Or do I need to add separate vias to each cap.