Below shows SCLK, MOSI and CS(\SYNC) lines for my SPI from a logic analyzer:
I use a Nucelo board as master to control this DAC(slave) via SPI. I didnt receive the DAC yet and trying to set the SPI.
And here below is an example code for the above timing diagrams:
while (1)
{
HAL_Delay(1000);
value++;
if(value>=496)
{
value=485;
}
SPIoutputBuffer[1] = (char)(value >> 8);
SPIoutputBuffer[2] = (char)(value & 0x00FF);
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_4, GPIO_PIN_RESET);
HAL_SPI_Transmit(&hspi3, (uint8_t *)SPIoutputBuffer, 3, 1);
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_4, GPIO_PIN_SET);
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
From the logic analyzer, I can measure that the SPI transmission begins 5us after CS goes low and CS goes high 15us after SPI transmission ends.
The DAC's required timing diagrams given as follows:
My questions are:
1-) I use HAL_GPIO_WritePin(CS low) and next line HAL_SPI_Transmit and next line HAL_GPIO_WritePin(CS high). But what could be the reason that there is so much delay between CS high/low and the SPI transmission in my case? How could those delays be reduced?
2-) In my case the SPI transmission begins 5us after CS goes low and CS goes high 15us after SPI transmission ends. Does that satisfythe timing requirements in the datasheet?
