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I have already successfully simulated a three-phase rectifier on simulink. However, I wish to implement the same on LTspice because I would have liked to see the effect of using non-ideal components. In order to make it easier and avoid whole control and feedback implementation, I imported the switching pulses datapoints from my simulink simulation into Ltspice and given them to ideal switches as shown below(for now I am starting with ideal components). enter image description here

However, I am not getting the expected results. I expect a steady DC output voltage of 600V as I had obtained in my simulink simulation yet I am getting something like this:

enter image description here

Please point out what might be the possible reasons for this and how to solve this issue!!

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    \$\begingroup\$ What are the parameters for the control voltages (V4 to V9)? \$\endgroup\$
    – devnull
    Apr 1, 2022 at 18:32
  • \$\begingroup\$ @devnull they are datapoints of PWM pulses imported from simulink model which worked. \$\endgroup\$ Apr 1, 2022 at 19:36
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    \$\begingroup\$ Are you sure the hysteresis voltage on the switch should be negative? I'm not sure, just asking why you set it that way. Also, where are the plots of all the signals? You're just looking at the output - come on, it's SPICE, looking at more voltages is free! \$\endgroup\$ Apr 1, 2022 at 23:49

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Break down the problem: separately, plot each controlling source, and compare it with Simulink. When all 6 match, then you know the controls are good. Then make sure the controlling pulses are at least between 0.1 and 0.9 (the minimum range should be from vt-|vh| until vt+|vh|). Not lastly, check that the three phase sources in Simulink have the same phase shift, because what I see in your LTspice (note the spelling) is a negative sequence. If what you need is a positive sequence then you need 0, -120, and 120 degrees (or 0, 240, 120).

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    \$\begingroup\$ Also, 1u timestep might be a bit overdone, but that depends on what exactly you're after. If it's only a test, even no timestep will be just fine. \$\endgroup\$ Apr 1, 2022 at 20:44
  • \$\begingroup\$ Thank you very much! It was the phase error, I feel very silly for missing that. It's working perfectly now. \$\endgroup\$ Apr 2, 2022 at 6:00

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