LTSpice simulation with multiple comparators causing problems

Question

I'm trying to build a circuit that limits the current flowing to the load at a specific level. To do this, I'm using a current sensing IC (INA138) and comparators to provide the necessary logic. However, when I try to use more than one comparator in the logic, the simulation bugs out and is never able to load. EDIT: by "bug out" I mean that the program continues iterating infinitely upon attempting to simulate.

This is a simplified version of my circuit with one comparator: (it works fine if the load is set to a level where the current sensing doesn't need to kick in - this is why I'm using a load of 2R).

And this is with two comparators:

This is a simplified version of my circuit; I need to perform other tasks preferably with other comparators before the logic signal is sent to the NPN BJT to open the PFET, so the second comparator probably doesn't look like it's particularly necessary there (I could upload a version of my circuit that's more elaborate for that part but I'm not sure that level of detail would be clarifying).

Is it possible to do what I'm trying to do with multiple comparators feeding into each other? Or should I set up some other elaborate solution involving PFETs or something?

Output between the comparators:

The INA138 is a non-standard LTSpice component. I've made it available at: https://easyupload.io/2e1l4j

EDIT: user @Kuba hasn't forgotten Monica suggested I used some kind of switch to shut off the load. Would this work?

Circuit:

Would this work in principle so long as the capacitor is charged? I've designed it to discharge over 2 seconds but how would I ensure sufficient charge on the capacitor at circuit start?

Answer 1

The “weird oscillating output” is because it looks like the circuit is an oscillator with positive feedback. You designed it to be that way. The simulation is correct.

It also has nothing to do with presence of multiple comparators, just that you happened to design a circuit that oscillates when you add the 2nd comparator :)

There’s no stable DC operating point. Thus, if you precede the transient simulation with a DC solution, as is the default, it’s not supposed to ever succeed – that would be a gnarly bug. So it “iterates” forever, by design.

Just think about what you want it to do. A load goes over the current limit. So you shut the load down. What happens to the current then? It goes back to 0. Hey, no more overload. So you turn the load back on. And the cycle repeats.

You need to do something else, for example:

1. Latch the shutdown state until power off.

2. Instead of shutting the load, regulate the current linearly, but monitor the mosfet temperature. If it gets too hot, shutdown until power off.

3. Latch the shutdown until some reset action is performed, like disconnecting the load. You could use a simple impedance sensor to detect presence of a load. Push VCC via a 5M resistor to the load, and if it’s below VCC-10mV, treat the load as plugged in. Reset the shutdown latch when the load is removed, or a “Reset” button is pressed, etc.