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I have a PHY-CHIP with XAUI Interface connected to a A7-FPGA-CHIP(GTP). My schematics say I should reconfigure the "polarity and order" of my incoming and outgoing xaui - GTP Pins.

Here an example:

  • phy-xtx0_3N is wired to mgt216RX0P
  • but I think it should be to mgt216RX3N

I tried to change my xdc file and I tried to connect the signals in my top lvl.

I get one critical warning like this:

[Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports,  port a7_mgt216_rx_p_i[0] can not be placed on PACKAGE_PIN B11 because the PACKAGE_PIN is occupied by port a7_mgt216_rx_n_i[3] ["ts.xdc":25]

But I get like 8 critical warnings of this :

[Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports,  port a7_mgt216_rx_n_i[0] can not be placed on PACKAGE_PIN A11 because the PACKAGE_PIN is occupied by port a7_mgt216_rx_n_i[3] ["/home/constraints.xdc":26]

Questions:

What do you think:

Is it possible to change it or is it bad luck if its not wired correctly on the pcb? Is there another XAUI example I could try? I don't think so right? Its rather a very special topic right? In best case I could fix the bad connection between GTP and XAUI right?

what may not work:

xaui< -> transceiver<-> **change order of signals** <-> phy

possible solution:

xaui <-> **change order of signals** <-> transceiver<-> phy

phy-gtp-xaui lol i thought is easy but xaui is connected really strange to the transceiver. I thought it would just connect "directly" but there is something in between so I maybe cant change it that easy.

enter image description here here you can see the entering connections from the phy to the gtp.

Tx0 and Rx2 go to GTP Channel 1 and from there to the XAUI I am really not sure if this will work xD I counted them n/p swapped pairs: 3

sorted connection

can I change this connection from GTP to XAUI Core easily?

CAN I CHANGE THIS?

What do you think about TX/RX POLARITY it should switch some TX n/p and RX n/P of Channels. Only problem would be mixed up lanes from XAUI to GTP^^

I need to check the Transceiver connections. How is a transceiver normally connected to incoming / outgoing data...

Update:

change the *xci file now:

https://support.xilinx.com/s/article/57546?language=en_US

mgt_txdata_reord(216+15 downto 216) <= mgt_txdata(15 downto 0);

mgt_txdata_reord(316+15 downto 316) <= mgt_txdata(31 downto 16);

mgt_txdata_reord(116+15 downto 116) <= mgt_txdata(47 downto 32);

mgt_txdata_reord(016+15 downto 016) <= mgt_txdata(63 downto 48);

mgt_txcharisk_reord(22+1 downto 22) <= mgt_txcharisk(1 downto 0);

mgt_txcharisk_reord(32+1 downto 32) <= mgt_txcharisk(3 downto 2);

mgt_txcharisk_reord(12+1 downto 12) <= mgt_txcharisk(5 downto 4);

mgt_txcharisk_reord(02+1 downto 02) <= mgt_txcharisk(7 downto 6);

What do you think about it?

..

(I need also to change the polarity now of some lanes, with the config vector of the transceiver ..

maybe thats all

haha)

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1 Answer 1

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Tranceivers are generally on dedicated pins so you cannot just remap them like that.

You might, maybe, be able to do your second option, but may need a register between the lut and the transceiver to meet timing if you need an inversion.

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  • \$\begingroup\$ Ah the PHY is there as a chip. And it is connected to A7 FPGA. But it even sais in the schematics, that I should change some order xD So I wonder if its that easy \$\endgroup\$
    – pgapga
    Commented Apr 6, 2022 at 11:11
  • \$\begingroup\$ I should check the pin connection again. Sometimes its easier then it looks like. But if I really need to check the LUTs and the timing it might be complicated right? \$\endgroup\$
    – pgapga
    Commented Apr 6, 2022 at 11:35
  • \$\begingroup\$ I did of course mean transceivers are on dedicated pins. \$\endgroup\$
    – Dan Mills
    Commented Apr 6, 2022 at 11:51
  • \$\begingroup\$ yes . I think I already understood :) Someone right now told me, he had the same issue and had to do make a new board/pcb xD \$\endgroup\$
    – pgapga
    Commented Apr 6, 2022 at 12:07
  • \$\begingroup\$ TX/RX POLARITY may be could to change polarity.. what remains is the mixed up lanes that dont follow a order and cant be changed by the wizard. ... I should go deep into the xaui core design and check how transceiver send/ receive data normally. \$\endgroup\$
    – pgapga
    Commented Apr 14, 2022 at 4:38

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