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Reference

I refer to the article "Grounding in mixed-signal systems demystified, Part 2”, written by TI engineers Sanjay Pithadia and Shridhar More. Link here: https://www.ti.com/lit/an/slyt512/slyt512.pdf

On page 7, paragraph 2, it says:

“The AGND and DGND pins should be connected to each other and to the analog ground plane, and the analog and digital ground planes should be connected individually back to the power supply. The power should enter the board in the digital partition and be fed directly to the digital circuitry, then filtered or regulated to feed the analog circuitry. Then only the digital ground plane should be connected back to the power supply.”

The last sentence seems to contradict the first sentence. I have highlighted the two in bold.

Question 1 So, should digital ground plane be the ONLY one connected back to PSU ground, or should I connect both to PSU ground?

Question 2 Should the analog LDO (i.e. A_VDD power supply) be placed over the digital ground plane area? Over the analog ground plane area? Or neither, and with a trace from one of the above, but with no ground pour below?

NOTE My question relates to a single 2 sided PCB with 2x ADC chips on the top layer. Incidentally they are the MCP3561R sigma-delta ADCs. I am aware this section of the article is not exactly the same as my application.

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Grounding in mixed-signal systems demystified

"Demystified" with small print disclaimers applied :)

Your goal is to contain AC and DC current loops so that the voltage drops they develop across the ground plane impedances aren't adding up to the effective input voltages fed to various inputs (of the gain stages, ADCs, output amps, etc.)

Adding slots or otherwise physically separating the ground planes is just one of many means to achieve such containment.

Any work in this area should first quantify to an extent what sort of currents, frequencies, and parasitic impedances we have to deal with. Then estimate the worst-case "noise" or unwanted coupling from those current loops to sensitive nodes. Then decide how to route those currents so that they don't cause problems. Such routing and containment may involve adding cuts to ground planes, relocating components, overlapping current loops so the fields they produce cancel out (even if partially), etc.

should digital ground plane be the ONLY one connected back to PSU ground

Usually, but it really depends on what other connections there are. A system block diagram depicting all external I/O to your system (power, digital and analog) is necessary to provide any guidance in this respect.

The starting point is always a single uninterrupted ground plane and well identified current loops that are arranged to circulate locally, affecting only small areas of the reference planes (be it ground or power).

You may often find that the performance is well within the requirements (which you didn't state, BTW).

Such a plane necessarily has the lowest bulk impedance between any two points. As you start removing copper, you trade off impedance for potential containment and isolation of interfering signals. As with all trade-offs, if you can avoid it, so much the better.

Should the analog LDO (i.e. A_VDD power supply) be placed over the digital ground plane area? Over the analog ground plane area? Or neither, and with a trace from one of the above, but with no ground pour below?

The LDO can straddle the two planes. The connection between the two can be made at the ADC, or at the LDO, or somewhere in-between. The LDO should be then very close to the ADC.

With a 2-layer board, such designs become "interesting" and you should not expect the first version to work as well as it ultimately could. In absence of sophisticated modeling tools and battle-hardened intuition, you'll have to experiment and then connect the experimental results to theory, i.e. understand what parasitic impedances play a role and why.

You'll want to set yourself up for precision differential voltage measurements, i.e. build (or buy) a differential wideband preamplifier you can use to measure small voltage differences between nominally "connected" points in your circuit. The preamp bandwidth needs to be solid - 100MHz would be nice, 10MHz would be better than nothing.

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  • \$\begingroup\$ That was an absolutely fantastic response. Thank you. Basically, as a well-known social network might say, "it's complicated". I already had version 1 of the board back and assembled, and I am not getting the SNR quoted by the datasheet. I believe I have fixed the main culprit already, which was my high speed SPI lines crossing over the top of DGND to AGND. I just rotated the parts, and the analog inputs now come into one side of the ADC and the SPI come into the other, they are kept separate. For now I have already started down the route you suggested, which is to create 4 [cont] \$\endgroup\$
    – hazymat
    Apr 6, 2022 at 13:22
  • \$\begingroup\$ [cont] different versions of the board: a strange looking star ground arrangement with analog supply outside the ground plane and connected by a thick trace to the star point. Second version simply shares the ground (no split analog / digital ground). Third version has split grounds but the AGND and DGND legs of my two ADCs tied together, and fourth version some permutation of the above. I don't have modelling software or even a pre-amp - only a reasonably ok scope, so I'm relying on the output of the ADC to give my results in terms of signal to noise. \$\endgroup\$
    – hazymat
    Apr 6, 2022 at 13:25
  • \$\begingroup\$ Start easy: battery powered, separate power sources for the MCU and ADC - only connected by the shared ground plane, and purposefully limited bandwidth of digital signals that go from MCU to ADC (use the largest series isolating resistors that maintain sufficient signal integrity - to minimize AC currents flowing back from ADC to MCU). That may well give you what you want. Then you can morph that to the final form, and see at what step things turn for the worse. ADC itself is a poor measurement tool: it doesn't tell you where the problem originates. You just know some pins see interference. \$\endgroup\$ Apr 6, 2022 at 13:32
  • \$\begingroup\$ Thanks, that's mostly what I have done. Battery power source. Even took it into the garden away from buildings to take measurements, then pause for 2 mins whilst I run inside, connect to network, and dump the readings! Also yes I have used 10R resistors on the SPI lines (placed nearer the MCU than the ADC, hope that's correct, probably doesn't matter?) as suggested by data sheet. I agree ADC is a poor measurement tool as it doesn't show me where any problems come from. The deeper I go into this the more I will need to investigate alternatives for identifying problems I think. \$\endgroup\$
    – hazymat
    Apr 6, 2022 at 13:39

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