Examining internal signals
You have to bring internal signals of interest out on top-level ports for a testbench to be able to access them.
This is a strength of VHDL. Architecture contents cannot be accessed by other architectures, only through the ports made public in an entity.
You can add a wrapper top-level entity/architecture around your current top-level design entity. The latter would become the second-level entity. The top-level entity would contain ports for the pins of the target device only. The second-level entity can contain the same ports plus your test interface ports. The testbench would instantiate the second-level entity. The synthesis tools would use the top-level entity and all below.
The downside of the wrapper is that you're not simulating the actual full design. This may be insignificant in a personal project but it's not allowed for design qualification by many companies/organisations because you're not testing the full design.
You can also have top-level ports for test values that go to unused and unconnected pins on the real board. Make sure you enable internal pull-ups on such unconnected input pins.
Changing internal signal values
Changing an internal signal cannot be done from VHDL unless you add a mechanism to your design to do so from the top-level ports.
You can take a register's value from a constant defined in a package. Then you can have two versions of the package, one for synthesis, one for simulation, with relevant values for testbench or target device. It doesn't allow for testbench control of the values, though. Again, formal design qualification procedures may not allow this.
In ModelSim, you can use a
force command to change internal flip-flop values. But its execution would have to be synchronised with the right moment(s) in your testbench's execution, which usually makes it impractical.
Don't use default signal values
You should never use initial values for signals and instead implement a reset, as explained in this answer. If you add a reset input port, that can be controlled by the testbench.