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I was referring to this question, but I had a confusion due to the concept of programmable logic devices. Image from UW page 7. Here the OR section can have up to 8 inputs to it. I'm confused about how the PL hardware avoids the transistor level problems while having so many inputs to a gate.

PLA

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  • \$\begingroup\$ A "gate" is an abstraction. You can implement an OR gate with 1000 inputs out of <lazy to calculate number> 2-input OR gates. \$\endgroup\$
    – Eugene Sh.
    Apr 7, 2022 at 16:47
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    \$\begingroup\$ Right, but those subsequent stages of logic (might) increase the delay, which is not a good news. \$\endgroup\$
    – lousycoder
    Apr 7, 2022 at 16:51
  • \$\begingroup\$ OR is a parallel operation \$\endgroup\$ Apr 7, 2022 at 16:57
  • \$\begingroup\$ This is a separate question. If you want to ask how to implement a many-input OR gate in a way that will not affect the delay - ask it. \$\endgroup\$
    – Eugene Sh.
    Apr 7, 2022 at 16:57
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    \$\begingroup\$ @TonyStewartEE75, making the OR gate wider increases the propagation delays through all of it towards its single output. Plus increased routing delays from what's feeding it. \$\endgroup\$
    – TonyM
    Apr 7, 2022 at 17:37

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Standard cell libraries tend to limit the number gate inputs to 4. More than that increases delay, and doesn’t fit well on the cell placement grid.

What you show is a higher-level macro called a Programmable Logic Array, or PLA, which can implement wider input functions.

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  • \$\begingroup\$ As I don't know the internal structure of the PLA here, how do they support wider input functions and if they use the n-stage cascading of OR gates, how do they reduce the delay? FPGA although structurally different, is used for low latency applications, right? Don't have the exact value for low latency, but gate stages aren't good for low latency, right? \$\endgroup\$
    – lousycoder
    Apr 8, 2022 at 4:36
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    \$\begingroup\$ PLAs support a generalized ‘sum of products’ form using shared wiring to implement wide AND followed by OR. Their main advantage is a regular structure that not only can implement large functions, but they’re easily modified. FPGAs use lookup tables to do something similar. \$\endgroup\$ Apr 8, 2022 at 16:10
  • \$\begingroup\$ can/is this shared wiring be used in the current compute hardware which operates at GHz frequency? \$\endgroup\$
    – lousycoder
    Apr 9, 2022 at 8:13
  • \$\begingroup\$ And does this shared wiring help cram more logic per unit area, while not disturbing other factors and without introducing new problems? \$\endgroup\$
    – lousycoder
    Apr 9, 2022 at 8:27

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