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In PCI bus introduction materials, especially when talking about the load capacity of the PCI bus, it's often stated that a PCI card inserted into the PCI slot is actually acting as two loads on the bus, one is the card itself, the other is the slot in which the card is plugged in. Why is that?

For example, in page 16:

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of the book: enter image description here

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2 Answers 2

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The parasitic capacitance of the PCI standard edge connector system is similar to the input capacitance of the ASIC/FPGA that implements the PCI function, and its associated traces.

The PCI slot connector system trades off some performance for low cost and acceptable price-performance ratio.

If you wanted to use non-standard, higher-performance connector systems, you could probably reduce the slot parasitics to 0.3-0.5 of a PCI load, perhaps better if a redriver was used at each slot.

On a parallel PCI bus, you can connect about 10 ASICs directly on the motherboard, with good wiggle room left, whereas 5-6 devices are a maximum if they are on plug-in cards. This informs system design: if you need more than 5-6 devices on the bus, you need to move some of them from the slots to the motherboard, or you need to use more expensive connector systems, or you need to add another PCI bridge.

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If the total load capacitance is too high, the signals cannot switch fast enough. (It is not possible to just use stronger drivers because they would increase switching noise too much if the bus is not actually loaded.)

A "PCI load" is just a simplification of measuring the capacitance. A PCI connector has a certain capacitance (due to its geometry and the length of the traces), so it must be included in the calculation.

If you solder a PCI chip directly on the motherboard, you have a lower capacitance, and you can use more devices.

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    \$\begingroup\$ Thanks @CL. A related question: if the bus has several un-populated slots, do those empty slots affect the signal integrity between the PCI host and the populated pci card? Thanks again. \$\endgroup\$
    – bruin
    Apr 9 at 15:40
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    \$\begingroup\$ @bruin Yes, they look like stubs off the bus (Even if physically placed after the populated slot). This is one reason why the point to point PCIe (despite its insane speed) is generally figured to be MUCH easier to route then PCI was. Wide, parallel multidrop bus, just nope, even DDR3 is less painful. \$\endgroup\$
    – Dan Mills
    Apr 9 at 16:11

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