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I am new in Verilog language. I am trying to understand the basics. There is this question where the input is a 6-bit number named IN and the output is a 1-bit number named OUT. When IN < 29, OUT is one. Otherwise OUT is zero. I have already written the code, and I am sure it is correct; however the simulation does not show anything. I have been trying to figure out what's wrong for a while now. I would appreciate any help I can get with this. My testbench goes until IN = 6'd29;.

    `timescale 1ns / 1ps

module lab1(input [5:0]IN, output reg OUT);

     always @ (IN)
     begin
        if (IN < 6'd29)
            OUT = 1'b1;
        else
            OUT = 1'b0;
        end
    //assign OUT = ~IN[5] & ~IN[4] | ~IN[5] & ~IN[3] | ~IN[5] & ~IN[2] | ~IN[5] & ~IN[1];
    //assign OUT = (IN < 6'd25) ? 1'b1 : 1'b0;
endmodule
`timescale 1ns / 1ps

module lab1_tb;

    // Inputs
    reg IN;

    // Outputs
    wire OUT;

    // Instantiate the Unit Under Test (UUT)
    lab1 uut (
        .IN(IN), 
        .OUT(OUT)
    );

    initial begin
        // Initialize Inputs
        IN = 6'd0;
        #10;
        IN = 6'd1;
        #10;
        IN = 6'd2;
        #10;
        IN = 6'd3;
        #10;
        IN = 6'd4;
        #10;
        IN = 6'd5;
        #10;
        IN = 6'd6;
        #10;
        IN = 6'd7;
        #10;
        IN = 6'd8;
        #10;
        IN = 6'd9;
        #10;
        IN = 6'd10;
        #10;
        IN = 6'd11;
        #10;
        IN = 6'd12;
        #10;
        IN = 6'd13;
        #10;
        IN = 6'd14;
        #10;
        IN = 6'd15;
        #10;
        IN = 6'd16;
        #10;
        IN = 6'd17;
        #10;
        IN = 6'd18;
        #10;
        IN = 6'd19;
        #10;
        IN = 6'd20;
        #10;
        IN = 6'd21;
        #10;
        IN = 6'd22;
        #10;
        IN = 6'd23;
        #10;
        IN = 6'd24;
        #10;
        IN = 6'd25;
        #10;
        IN = 6'd26;
        #10;
        IN = 6'd27;
        #10;
        IN = 6'd28;
        #10;
        IN = 6'd29;
        #10;
    end
    
        
endmodule
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0

1 Answer 1

4
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Many simulators generate a warning message for your code. For example, on EDA playground, I see:

        .IN(IN), 
             |
xmelab: *W,CUVMPW (./testbench.sv,14|13): port sizes differ in port connection(1/6) for the instance(lab1_tb) .

The solution is to change:

reg IN;

to:

reg [5:0] IN;

Perhaps your simulator does generate a warning, but it wasn't obvious to you where you should look for it. Note that your code is legal Verilog syntax, which is why you do not get an error.


Here is a more compact way of writing your code, using a for loop for the input:

`timescale 1ns / 1ps

module lab1 (input [5:0] IN, output OUT);
    assign OUT = (IN < 6'd25);
endmodule

module lab1_tb;

    // Inputs
    reg [5:0] IN;

    // Outputs
    wire OUT;

    // Instantiate the Unit Under Test (UUT)
    lab1 uut (
        .IN(IN), 
        .OUT(OUT)
    );

    integer i;

  initial begin
    // Initialize Inputs
    for (i=0; i<30; i=i+1) begin
        IN = i;
        #10;
    end
  end
          
endmodule
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