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I want to make a retro computer around a 6809E and a CPLD. It occurs to me that the physical layout/design of this board would be nearly identical for all the 40 pin, 8 bit CPUs except for power and ground. I want to use a Lattice ispMACH 4000ZE for the CPLD (3.3V I/O, 5V tolerant) and primarily I'm interested in the Z80, 6502, and the 6809E. I'm not opposed to supporting other 5V, 40 pin DIP CPUs.

As an example I know that PROM programmers implement software selectable power and ground pins.

My experience is mostly software and digital logic. I suspect that this can be fairly easily implemented with some sort of pull up/pull down transistor circuit, but I don't know enough to find an explanation / example.

Thank you in advance!

EDIT: Additional info that may be useful.

  • The CPLD supports 3.3V LVTTL levels with 5V tolerant inputs so I don't need to level shift signals between the CPU and the CPLD.

  • I'm planning on using a PC ATX power supply, so I have +3.3, +5, +12 and -12 easily available

  • I know I could use jumpers to accomplish this, The reason I'm looking at doing this electronically as opposed to physically is that there are a limited number of pins that I need to support (5 power, 4 ground). I'm not looking at having a completely generic solution.

  • The list of CPUs I look at:

    • Motorola 6800
    • Motorola 6809/6809E
    • Hitachi 6309/6309E
    • Zilog Z80
    • Mostek 6809
    • Mostek 65816
    • Intel 8085
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  • \$\begingroup\$ I have pondered doing much the same thing. My approach was to have specific pcbs for each of the micros with a common high density connector to the fpga board. If you've ever looked into those universal programmer units you'll see they are full of transistors, resistors etc to perform the magic. What you want to do is achievable, but will require a bit of thinking. Me, I'm lazy and will go for the 'easy' solution. With the cost of pcb fab these days, my suggestion is cheap. Each board can have specific labelling, so it is obvious to see which cpu you've got configured. \$\endgroup\$
    – Kartman
    Apr 10, 2022 at 2:40
  • \$\begingroup\$ The only reason I'm even considering it is that I'm only looking at a handful of lines. No way I'd think about doing all 40. \$\endgroup\$
    – Lee Morgan
    Apr 10, 2022 at 3:07

3 Answers 3

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  1. A PMOS/NMOS pair for every pin, to connect it to VCC/GND. Those typically are best obtained as H-bridges that integrate mosfets and interface to logic level control inputs.

  2. Two rotary decimal switches (like DIP switches but look like potentiometers) for each VCC and GND pin selection.

  3. 8 BCD-to-1-of-10 decoders with enable input to drive the mosfet gates using switch input.

Each H-bridge could drive two pins. You'd need 20 H-bridge chips for full 40-pin configurability. L9110H is a nice 8-pin DIP device that would likely work here.

It wouldn't be hard to make it work on all 40 pins. You can of course only populate a subset, but I'd put footprints for all 40 on the PCB. Make sure to clearly label each footprint with the corresponding pin number, in a larger, easily visible font, on the silkscreen.

Instead of 1-of-10 decoders, you can use HEX rotary switches and 1-of-8 decoders. That's 12 bits total to select VCC and GND, vs 16 bits if using BCD. Those bits could also be driven by the PLD/FPGA, making the rotary switches optional.

You can connect a two-color SMT LED next to each of the 40 pins, and connect it to the digital inputs of corresponding half bridge. The LED will be off when the pin is not driven to VCC/GND, otherwise its color will indicate GND vs. VCC.

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The common solution in such cases (ICs with different voltages) is to use level translators. An example would be the 74LV8T245 for an 8-bit bus. You generally don't want to change the ground reference of a design, unless you absolutely have to.

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  • \$\begingroup\$ I don't need to level shift the I/O. The CPLD in question is 5V tolerant and 3.3V LVTTL. Specifically I'm looking at Vcc/Vdd and Vee/Vss/GND. So I'm looking at being able to have a circuit that will drive to VCC/GND or ti-state. I'm intending to use a standard PC ATX power supply, so I have +/- 12V available if that helps. \$\endgroup\$
    – Lee Morgan
    Apr 9, 2022 at 21:59
  • \$\begingroup\$ You’ll probably get flaky operation driving old stuff with 3V logic levels. I’d be using some level shifters. That itself adds a layer of complication coping with various pinouts. Then there’s the other issue of powering your circuit so it can select the pwr/gnd pins. Chicken n the egg! \$\endgroup\$
    – Kartman
    Apr 10, 2022 at 7:22
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The easiest way is probably to have 2 3 x 20 headers (one on each side of the chip) and manually install jumpers on the pins that need to be Vdd and GND.

Otherwise you're going to have to determine the maximum current requirements (some of those old chips could draw well in excess of 100mA) and maximum voltage drop. Then maybe 80 transistors (eg. SOT23 MOSFETs) and some shift registers to control them. Or 20 dual pin driver ICs as used in ATE but they are very high performance typically and do not come cheap.

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  • \$\begingroup\$ I have a layout that uses jumpers. One of the reason I thought this is doable is that there are only 5 pins that are used for power and 4 pins for ground across the CPUs I looked at. \$\endgroup\$
    – Lee Morgan
    Apr 9, 2022 at 23:16

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