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I have a spectrum analyzer that's primarily supposed to be used for RF measurements.

It lists an input limit of +30dBm max, and 0V DC, and has a 50Ohm impedance. My RF signal generator speaks the same language: you specify the output amplitude in dBm, and whatever number I select on the generator matches what the analyzer sees.

The analyzer has a frequency limit of 100Hz at the low end. I want to use it to measure the spectrum of signals that come out of an FPGA that are in a range of 0 to 10MHz. The FPGA IO is configured to be a 3v3 LVCMOS output.

What do I need to do to make sure I don't destroy the spectrum analyzer input circuit?

It's clear that I need to insert a series capacitor to remove the DC component, either by putting a cap on my board or by inserting an SMA DC blocker on the measurement cable.

I know the +30dBm corresponds to 1W, which is much higher than the power that can come out of an FPGA digital output.

But I'd like to get the mathematics and basic understanding right: how do I convert from an FPGA IO drive strength to dBm?

As an example, let's take a MAX10 FPGA IO configured as 3v3 LVMOS output with a 2mA driving strength. What's the corresponding dBm?

Is it just 3.3 * 0.002 = 6.6mW, which converts to 8.2dBm?

Or is there more to it, e.g. because there's also a 50 Ohm impedance to take into account somewhere?

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    \$\begingroup\$ I would not trust the behavior of the IO pin to be "normal" when it is connected just to a 50Ω load. The datasheet says it can supply 2mA when VOH is at (VIO-0.2), which would imply a minimum load resistance of 1550Ω. So I would say you should put a high value resistor -- maybe 2kΩ -- in series with the IO. It will attenuate the signal into the spectrum analyzer a lot, but that's no big deal since spectrum analyzers do great with small signals. And the behavior of your I/O pins will probably be much more representative of "real" operation. \$\endgroup\$
    – Mr. Snrub
    Apr 10, 2022 at 8:13

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If your '2 mA driving strength' really means that your FPGA output behaves like a +/- 2 mA current source (which I doubt, in detail at least), then it could be connected directly to the spec ana input with a series DC blocking capacitor.

The calculation would go thus. Power into the 50Ω input of the analyser is \$I^2R\$ is 0.002 x 0.002 x 50 = 0.2 mW = -7dBm. That's the total power of the square wave. Most of this would end up in the fundamental, the rest of the power would go into the other odd harmonics. You might have some even harmonics visible, due to asymmetries in the squarewave.

I would be more inclined to program the output to maximum drive strength, so it behaves more like a voltage output, then use a series resistor and capacitor. You could use a 50Ω resistor, or one that's bigger.

If you used a 50Ω series resistor, then the FPGA output would be driving a total of 100Ω, and the +/- 1.65 V coming from it would drive +/- 16.5 mA into the spec ana, if it had sufficient drive strength. A bigger resistor would reduce the current. The \$I^2R\$ calculation is just the same, to give 13 mW or +11.3 dBm with 16.5 mA. Of course this sum assumes zero output impedance from the FPGA, which is not going to be true. Working back from a measurement of power on your spec ana might in theory allow you to estimate the extra output impedance of the FPGA, but the poor basic accuracy of the spec ana would make that very inaccurate.

A trick that mainly RF engineers use to probe circuits (also useful for high speed logic) is to use a series resistor in the 470Ω to 1kΩ ballpark, in series with a DC blocking capacitor, connected directly to a 50Ω coax cable going to a spec ana. This value of resistance is usually high enough to not trouble a logic or 50Ω impedance RF circuit too much, yet still give a reasonable amount of signal into the spec ana. Although the coax is not being driven from its characteristic impedance, the resulting probe is flat and well behaved because the coax is terminated by the spec ana input. The resistor end of the coax must be grounded very close to the point being probed.

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  • \$\begingroup\$ I was aware that the heavy load of the 50Ohm resistor would drop the output voltage of the driver, but it didn’t occur to me to just use max current alone and use P = I^2 x R (even if that might be overestimating the power.) I was indeed planning to put a larger resistor in series, just to be sure. If I use, say, a 470 Ohm resistor, what would be the equivalent attenuation value in dB? \$\endgroup\$
    – Tom Verbeure
    Apr 10, 2022 at 14:03
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    \$\begingroup\$ @TomVerbeure Let's assume FPGA output impedance is 20 ohms, and the drive strength is adequate, so with a 470 ohm resistor and a 50 ohm load, the total resistance is 540 ohms. With a swing of +/- 1.65 V, we get a current of +/- 3.05 mA, and that into 50 ohms using I2R gives 0.46 mW = -3.3 dBm total power, of which the fundamental will be slightly less. \$\endgroup\$
    – Neil_UK
    Apr 10, 2022 at 14:10
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    \$\begingroup\$ @TomVerbeure In that case, any resistor smaller than 1k or so will run into a drive strength limitation. I wouldn't imagine that the outputs behave like a good current source, just limited enough to get controllable rise and fall times into lines with low stray capacitance. \$\endgroup\$
    – Neil_UK
    Apr 10, 2022 at 14:12
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    \$\begingroup\$ @TomVerbeure Use a CMOS buffer to get a voltage output if you want a decent output current, otherwise you're stuck with the limitations of that 2 mA \$\endgroup\$
    – Neil_UK
    Apr 10, 2022 at 14:16
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    \$\begingroup\$ @TomVerbeure Let's be clearer about that. Limited drive strength is precisely to limit the slew rate of an output. There is always some stray capacitance on an output. Unless all artefacts of the slew are over completely by the time of the next edge, what the previous bit was will affect the weight, the moment, the effective value of the following bit. This will distort what the FPGA thinks digitally about the bits that they are all exactly the same moment regardless of their neighbours. Sigma delta can deliver very high SNRs, you may notice even -100dBc distortion. \$\endgroup\$
    – Neil_UK
    Apr 10, 2022 at 14:58
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Drive strength is something defined is some fancy way, maybe while complying with VOH level definition. In short it's not something I'd rely on for this calculation.

Lucky enough you can stick on worst case and still have plenty of allowance.

If you imagine to simply have the 3.3V supply shorted onto the spectrum analyser 50ohm input you get approx 220mW or 23dBm.

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  • \$\begingroup\$ How did you get to that number of 220mW? \$\endgroup\$
    – Tom Verbeure
    Apr 10, 2022 at 13:55
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    \$\begingroup\$ It's just \$ (3.3\,\mathrm{V})^2/50\,\Omega \$ \$\endgroup\$
    – carloc
    Apr 10, 2022 at 14:14

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