# Noise of a precision/active rectifier

I am trying to build a precision rectifier circuit to implement AM demodulation in a sensor signal chain.

For now I have calculated the sum RMS noise of the total signal chain except that of the precision rectifier. I was ready to use a zero crossing detector but gave up because of the square wave phase shift. All I want to know is how can I calculate the noise of a precision rectifier, especially the equivalent thermal noise model of a diode.

In my application, the carrier wave frequency is 2MHz and the bandwidth is 10kHz after demodulation. After demodulation, the maximum input to the ADC (regard the ADC as noise free) is about 2V. I need to get 16 bit effective resolution so the peak to peak noise voltage should below 2V/2^16 which is about 30uv, then noise density of total signal chain noise is 30uv/sqrt(bandwidth)/6(6 is 3 sigma peak to peak voltage to RMS voltage) equals 50nv/sqrt(hz). The noise expect precision rectifier is about 20nv/sqrt(hz) so all noise density left to the precision rectifier is sqrt(50^2-20^2) = 45nv/sqrt(hz). As I know, moderN op amp can provide much lower noise density than this butcan modern diodes provide such low noise density?

No need for an analog demodulator. Run the ADC synchronously with the carrier at 2MHz or a multiple thereof. 4MHz will make antialiasing much easier. Get demodulation for free. There are lots of affordable 16-bit ADCs that will run at such a speed.

If there’s little noise in the signal, you can decimate directly prior to demodulation: sample at some fraction of the carrier frequency.

In either case, you’ll run a PLL synchronized to the carrier. This can be something simple. In a pinch a selected CD4046B running from 17V will do for 2MHz PLL, although I wouldn’t do that in production.

The PLL output can be divided down to get the decimated frequency you’d need. The divisor needs to be even. The phase reference has to be adjusted to get maximum amplitude. It’s better to have both 0 and 90 degree sampling clocks and do quadrature sampling, though. That’s what you’d get by sampling at 4MHz. To do IQ sampling with pre-decimation, you’ll be taking pairs of samples 1.25us apart, and a multiple of 5us periods between the start of each pair.

The timing signals can be generated with a timer fed from an external PLL. Many MCUs have enough on board peripherals to allow a PLL implementation in software, using an external phase comparator and VCO, but internal ADC and DAC to close the loop.

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The signal chain is usually designed so that the noise of the demodulator can be ignored when referred back to the input of the 1st stage.

Active rectifiers based on voltage-feedback op-amps aren’t great demodulators. They are adequate, but that’s all you’ll get, since their internal nodes get off-balance when the rectifier is blocked. You can use a current-steering active rectifier that converts the input voltage into a current that goes down one of two branches, selected by current polarity. Convert current in one branch to voltage and you can get ok active rectification.

For precision you can’t really beat a synchronous demodulator either done using switched capacitors or digitally, after acquiring the signal with an ADC.

For AM demodulation that doesn’t need an analog output, it’s best to do it digitally. Even then you will get better linearity dollar for dollar by going A/D, demodulator, filter, calibration, then D/A route. You can do it all analog, but it won’t be cheap in terms of either expertise needed to design one quickly, or your experimentation time getting it to work well.

You should be equipped to objectively measure the performance. Set up test equipment that lets you excite the input in time and frequency domains (eg step response vs small signal sine response) and measure the output

• Thank you for you answer! Actually I pretend to implement demodulation digitally but decided to do it in analog filed because of the high working frequecny. A 16bit adc will not work for my application since the ENOB of a 16bit adc may be as low as 14bit and to meet the noise requirement I am ready to use a 24 bit adc with decimated sampling frequency. In breif, 24 bit adc is not able to provide such high sampling frequency and according to what you mentioned, I should use bandpass signal sampling theorem in digital filed right? Commented Apr 12, 2022 at 2:41
• This is a narrowband application. You cut a tiny slice of the wide bandwidth of a fast ADC. This improves noise proportionally to the bandwidth ratio of signal of interest vs. ADC bandwidth. That’s what makes software defined radio work where you can’t even see the signal with your naked eye yet the digital filter - usually implemented with FFT - has no trouble recovering it. The noise of an adc-based solution will beat almost any analog solution in your particular case. Handily. Commented Apr 12, 2022 at 12:23
• A 14 bit enob applies to the full bandwidth of an ADC. If you have a 16MHz sampling ADC with 14 bit enob and only use 10kHz of its bandwidth, you’ll get a way better than 16-bit ADC equivalent. That’s how sigma-delta ADCs work. A 24 bit ADC does the same: samples at many MHz at low resolution in a way that keeps the noise out of the low frequencies, then filters and decimates data. You can probably get the AM demodulation you want with an off the shelf HF SDR radio, with SNR you need. Commented Apr 12, 2022 at 12:26
• And if you insist on an analog solution then make an actual mixer to demodulate. It’ll have as good a noise as you can make in analog world. Commented Apr 12, 2022 at 12:27
• Thank you , that helps a lot Commented Apr 13, 2022 at 12:16