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I have a schematic. Here is a section of it: enter image description here

The FETS are being driven by the chip to behave as ideal diodes. Plus two FETs in series to block current path when chip is in shut down stage.

I've seen most chips have the drain connected to the thermal pad and generally recommended to maximize the drain copper plane to reduce thermal impedance of the FET. Why the drain and not the source for removing heat? Also in regards to layout would it make sense to bring the source of the 4 FETs very close together and then connect with a small plane and use the remaining space on the board to maximize the area for drain? Or do I need to increase the plane size for the source too?

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I've seen most chips have the drain connected to the thermal pad and generally recommended to maximise the drain copper plane to reduce thermal impedance of the FET. Why the drain and not the source for removing heat?

The answer is simplicity itself; the drain region of a power MOSFET is by far the largest area/volume on/in the silicon die and therefore, allows the highest removal of heat: -

enter image description here

Image source.

would it make sense to bring the source of the 4 FETs very close together and then connect with a small plane and use the remaining space on the board to maximise the area for drain?

Yes, I'd do it that way.

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