# SystemVerilog output issue with "m" in a 5-to-1 Mux

I'm having an issue that I can't resolve on my own. I nested a 2-to-1 mux module inside of this 5-to-1, and no errors occur. Yet my output "m" will only load in certain conditions and is x for most others. Can anyone point me in the right direction here or point out what I'm doing wrong?

I attached the code in Quartus along with an image of the output in ModelSim.

You'll see below commented out code for the testbench. I've just been testing different cases trying to get it to work.

// This module represents a five-bit mux that allows us to select one of five inputs
// NOTE: the way the circuit is depicted does not allow for a five vector mux, thus only the select bit is an array

module Mux_5_to_1 (u, v, w, x, y, s, m);

input u, v, w, x, y;
input [2:0] s;
output m;
wire a, b, c;

// Going to use 2 to 1 mux module that references the work for modelsim; no assignment necessary. inputs are specific
Mux_2_to_1 unit0 (u, v, s[0], a);   // u and v
Mux_2_to_1 unit1 (w, x, s[0], b);   // w and x
Mux_2_to_1 unit2 (a, b, s[1], c);   // u & V and w& x
Mux_2_to_1 unit3 (c, y, s[2], m);   // all with y for m

endmodule

module Mux_5_to_1_testbench();

reg u, v, w, x, y, s;
wire m;

// Instantiation
// Mux_5_to_1 DUT(u, v, w, x, y, s, m);
Mux_5_to_1 DUT(.u(u), .v(v), .w(w), .x(x), .y(y), .s(s), .m(m));

initial begin

/*
// int k;
// int j;
s = 0;

for (int k=0; k<8; k++)
begin

{u,v,w,x,y} = $random; #80; for (int j=0; j<9; j++) begin {s} = j; #10;$monitor(u,v,w,x,y,s,m);
end
end
*/

u = 0; v = 0; w = 0; x = 0; y = 0; s = 000; #50;
u = 0; v = 1; w = 0; x = 1; y = 0; s = 000; #50;
{s} = 001; #50;
{s} = 010; #50;
{s} = 011; #50;
{s} = 100; #50;
{s} = 101; #50;
{s} = 110; #50;
{s} = 111; #50;

end

endmodule


Below is the example of output "m" having red lines (x cases)

The Mux_2_to_1 code is:

// This module represents a 2 to 1 Mux

module Mux_2_to_1 (x, y, s, m);

input x, y, s;
output m;

// wire

// x AND !s
assign M1 = (x & ~s);
// !s AND y
assign M2 = (s & y);
// both AND gates
assign m = (M1 | M2);

endmodule

module Mux_2_to_1_testbench();

reg x, y, s;
wire m; // functions with or without this line. Haven't figured out why it's necessary

// instantiation is necessary to actually load the module variables for testing. Won't through error without line but crucial.
Mux_2_to_1 DUT(.x(x), .y(y), .s(s), .m(m));
// Can also do "Mux_2_to_1 DUT(x, y, s, m);", We don't need to do the formatting to get the output.

initial begin
\$monitor(x,y,s,m); // Has output and is formatted as such in C language. Will output when ran in Matlab. ex: "formatting", variables

/*
x = 0; y = 0; s = 0; #50;
x = 0; y = 0; s = 1; #50;
x = 0; y = 1; s = 0; #50;
x = 0; y = 1; s = 1; #50;
x = 1; y = 0; s = 0; #50;
x = 1; y = 0; s = 1; #50;
*/

for (int i=0; i<9; i++) // WARNING: putting brackets for "for loop" causes compile error
begin
{x,y,s} = i; // {MSB, ..., LSB} = i ; this is converting to binary output across vars when cycling through i
#10;
end
end

endmodule

• Just saw it and updated with code. Apr 16 at 2:32
• meaning of comment unclear. Please update question if relevant (if not already done). Apr 17 at 12:54

When I run your code on EDA playground using the Mentor simulator, I see this warning message:

# ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (1) for port 's'.
The port definition is at: testbench.sv(18).


I see similar warnings with other simulators. Perhaps your simulator also generates a warning, but you did not know where to look for it. Many simulators create a log file by default, and warning messages are usually in the log.

The bit width of all signals need to match when making connections to module instances. In the Mux_5_to_1_testbench module, change:

reg u, v, w, x, y, s;


to:

reg u, v, w, x, y;
reg [2:0] s;


This fixes the unknown (x) value on the m signal.

• That makes a lot of sense! Thank you so much. Apr 16 at 21:58