I'm designing a PCB which involves integrating two microcontrollers - an ATSAMD51 (Cortex M4)-based Arduino, and a Raspberry Pi.

I need to connect a parallel bus of 10 signals between the two devices. These need to arrive at specific pins of the ATSAMD51 to take advantage of certain ALT_SEL functions it has.

A specific set of the Raspberry Pi pins also correspond to one of its SPI controllers. I've thought ahead to further applications that would be able to reuse these two reprogrammable devices in different ways, and as long as I'm designing a PCB, I'd like to build in a bit of future-proofing if I can. The 4 pins that correspond to the SPI bus on the Arduino are free. It occurred to me that I could fork four of the signals that the Pi could use as SPI, and wire them into the corresponding SERCOM pads of the SAMD51:

Raspberry Pi connected to ATSAMD51 by 10-line bus, with 4 lines connecting to additional ATSAMD51 connectors

In the primary application, SPI is not used, so those four lines will just be default-inputs and this is safe. Future-me would obviously be using MISO as an ATSAMD51 output, which means making sure its other corresponding ALT_SEL pad isn't also a driving output. I could just be super careful with my microcontroller software, but bugs happen... so I'd like to build in some safety if I can.

Can I just add resistors in front of the SPI pads? The ATSAMD51 can handle up to 2mA per pin, so worst case, one pad drives HI and one drives LO, and I need to divide 3.3V into 2mA or less. A 2.2 KOhm resistor would ensure these limits are enforced.

The circuit from above, with resistors protecting the SPI inputs

I know resistors will add a phase shift, but if they're on all four SPI lines, the SPI bus should remain synchronized. But will this cause other forms of attenuation or concern? Theoretically since it's all GPIO-to-GPIO, the current (and thus the voltage drop) should be fairly minimal. But I don't know what other issues this might cause, or whether this in and of itself may damage the connected devices.

(You may ask why not just use a different Pi SPI controller and run 14 traces; the answer is that I am using a 74CBTLV3861 bidirectional transceiver / bus switch to allow for these devices to be isolated and it has 10 through-lines; the extra 4 traces would mean adding yet another IC, which I'd prefer to avoid.)

Thank you in advance for your help!

  • \$\begingroup\$ PS - in case it matters, I plan to use a 4-layer stackup (signal/gnd -- gnd -- power -- signal/gnd) \$\endgroup\$ Apr 14, 2022 at 22:55
  • \$\begingroup\$ How about making this a stuffing option? Most board designers I know would do it this way: give the layout four 0Ω resistors (or better yet one quad-pack of 0Ω resistors) leading to the MOSI/MISO/SCK/CS lines, and another set of 0Ω resistors going to the standard I/O pins. When the board is assembled, you install the 0Ω resistors which correspond to the pins you'll actually be using, and the other resistors are left unpopulated. Does that work for your needs? \$\endgroup\$
    – Mr. Snrub
    Apr 15, 2022 at 7:23
  • \$\begingroup\$ What frequency do you intend to operate the SPI bus and parallel bus at? \$\endgroup\$
    – user4574
    Apr 15, 2022 at 14:39
  • \$\begingroup\$ @Mr.Snrub interesting idea but not what I was intending. My purpose is "if I want to reprogram this existing assembly in a way that uses SPI" instead of the 10-line port. So making an assembly-time decision to enable one or the other doesn't help; I'm trying to get more future-proof flexibility out of a post-assembly board if that makes sense. And user4574 to that extent, I don't have a target SPI frequency in mind; if adding resistors means "it works but only < 1 MHz" or some other limit, that is acceptable. \$\endgroup\$ Apr 15, 2022 at 21:24

2 Answers 2


Sufficiently large resistors are a sufficient protection, just pick some that limit current to an acceptable range, depending on your logic level. You can later replace them with 0Ohm resistors or put a jumper in parallel to short out the resistors if they are not used. In many cases SPI works just well with a few hundreds of Ohms in series with the outputs.


2k may have an effect on the SPI -- it depends on which sub-version of SPI you use: CPOL, CPHA polarities -- this affects the relative clock phase where data changes; if you get it wrong you could have subtle data bugs.

Also, note that SPI is bidirectional -- the delays in one direction may be different than the other (capacitance, wire lengths could be different).

If you are only worried about software bugs during development, then the I/Os will likely be able to handle brief port conflicts -- the resistors are unnecessary.

  • \$\begingroup\$ Thank you, these are helpful insights. About different SPI signaling mechanisms, since I don't have a specific requirement in mind, and both devices handle all modes, I'd be OK if I needed to experiment or restrict to one or the other polarity. \$\endgroup\$ Apr 15, 2022 at 21:27

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