Fine to share between several. If they're all in a row, probably just one each on the ends, or at positions 2 and 5 (so all are at most 1 unit away from a capacitor).
With a 4+ layer (ground plane) build, even fewer might be reasonable -- planes act as nearly ideal connections between vias.
There are two considerations: supply impedance, and load current. Well, it's one really -- but there are two sides to it.
- Bulk (AC) current handling.
The supply has some impedance Z, and any (AC) load current develops a voltage drop ΔV = ΔI Z due to that current. This can be hand-waved as the ringdown/settling response from a step load current, or more formally in the frequency domain as the impedance of the supply network.
When load currents are independent, they sum as independent noise (an RMS total) rather than adding up proportionally. As long as this supply ripple is low enough that the devices don't mind (depending on their PSRR or other requirements), you're fine sharing capacitors between them.
When the supply currents are dependent (as can happen say with groups of logic ICs all changing state on the same clock edge), you may need one capacitor each, or more, to keep the ripple down. Conversely, if you can phase-shift the currents to cancel out, you can reap substantial savings (such as with phase-interleave SMPS).
- Dynamic stability.
Particularly for analog circuits, the magnitude of current (and its rate of change) may be small, but it's the gain and phase that matters. Basically, devices can exhibit negative resistance at their supply pins, or similar effects when feedback to their inputs occurs. The supply impedance needs to be low enough, and flat / well-damped enough, to avoid oscillation.
Note that, anywhere the Z(f) curve is changing (sloping toward a peak or valley), it's also very reactive, and one of those peaks or slopes may give enough phase shift at just the right frequency to cause oscillation.
For #1, supply impedance needs to be low enough that the ripple produced by a worst-case change in load current is within reasonable limits. This includes sudden changes in currents, i.e. where the dI/dt matters, and so also includes low inductance. It may also include a well-damped supply, so that unlucky patterns (say that an MCU might draw) do not excite resonances.
For #2, simply having a low enough impedance will do, preferably with a resistive characteristic so that resonances are damped out. Note that simply dumping capacitance on is NOT a wise idea, necessarily: using overly low ESR parts exacerbates resonances between them, due to the small trace inductances connecting them together. It's better to use modest-ESR parts, like tantalum, electrolytic, polymer*, or just plain old ceramic with a resistor in series with it.
*Aluminum polymer caps generally have low ESR, but last I surveyed the market, they are available in a wide range of ESRs, that simply clusters lower. Conversely, tantalum are usually on the high side (say 0.1-1 ohm), but are available with less (especially tant polymer). Both ranges overlap, so take your pick. Don't worry about type, simply select the appropriate ESR.
So, for the ACS712, the bandwidth is quite low (they roll off at ~100kHz, and likely don't have much of any internal response above 10MHz, where they could oscillate), and the current draw quite modest (maybe 10s mA if you're loading the outputs heavily). You might well get away with no local capacitance (relying on the next nearest on the board), but a few local caps are fine, likely safe to do, and you can always try without them if you need to optimize down those couple cents of cost.
If these were say 1GHz GBW op-amps, the requirement would be more stringent for both reasons: you need to avoid resonances within the part's bandwidth (so, a couple GHz), and the load current is likely higher (say, driving 50 ohm transmission lines at some 100s MHz). For this case, local and compact capacitors (small chip, preferably wide-body, with short connecting traces) are desirable.
Note that trace inductance adds with pin, via and component body inductance, all being on the order of 1nH/mm length; using wide traces, components, etc. reduces this factor a bit, as does using multiple vias in parallel (such as flanking the pads of a chip capacitor). You would also require ground plane construction to use such devices.
Note also that there is a representative impedance that depends on capacitance and inductance. Say you have two 0.1uF ceramic chip capacitors connected in parallel, 1cm apart: there's approximately 10nH between them, and the series loop totals 50nF capacitance; this gives a resonant impedance of \$\sqrt{\frac{L}{C}}\$ or 0.44 ohm, at \$\frac{1}{2 \pi \sqrt{L C}\$ or 7.1MHz. If this resonance is critically damped (such as this much ESR being added to the loop), it has a peak impedance of 0.44 ohm. However, the average ceramic chip will have more like 0.1 ohm ESR, so there will be a significant impedance peak. This can be damped by adding the ESR, or replacing one capacitor, or connecting in parallel with it, with a type having this much ESR. The motif of long trace to a small local bypass cap, with a lossy "bulk" cap in parallel, is a common sight in power supply network design.
