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I am unclear who the NOR gate S-R latch works.

If the input of one depends on the output of the second one, and vice versa, no output signal can be generated until we have a single gate output.

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if input of one is depandant of output of second and vice versa.

It isn't. With the input levels shown, the upper NAND gate's output can be either 1 or 0, but the lower NAND gate's output must be 1. That means the upper NAND gate's output will be 0.

Where it gets interesting is when both inputs are 1. Then the flip-flop will hold whatever state it had when one input was 0.

But what if both inputs are 0? In that case both outputs must be 1. Making one input high again would allow the other input to set that state. If both inputs are made high at exactly the same time then the state 'flipped' to will be random.

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