On a LTC3886-1 I can read this:
I see that all open-drain outputs are tied to VDD on the following application schematics:
Is there a reason why pull-ups seem required when the output is not used?
On a LTC3886-1 I can read this:
I see that all open-drain outputs are tied to VDD on the following application schematics:
Is there a reason why pull-ups seem required when the output is not used?
Well for one, there is a statement on the description of the pin itself (emphasis mine):
SYNC (Pin 13): External Clock Synchronization Input and Open-Drain Output Pin. If an external clock is present at this pin, the switching frequency will be synchronized to the external clock. If clock master mode is enabled, this pin will pull low at the switching frequency with a 500ns pulse width to ground. A resistor pull-up to 3.3V is required in the application.
The pin can act as output and input. Based on that description leaving the pin floating might cause it to pick up noise and try to synchronize to that noise.
The LTC3886 will automatically accept an external SYNC input, disabling its own SYNC drive if necessary. Whether configured to drive SYNC or not, the LTC3886 can continue PWM operation using its own internal oscillator if an external clock signal is subsequently lost. The device can also be programmed to always require an external oscillator for PWM operation by setting bit 4 of MFR_CONFIG_ALL_LTC3886. The status of the SYNC driver circuit is indicated by bit 10 of MFR_PADS.
So leaving it open sounds like it might cause some hick-ups in operation.