Biasing of an NMOS transistor

Question

I want a current of 100mA to flow through a transistor. For that, I polarize it with a voltage divider.

The transistor I use is the BS270. According to its data sheet, for a current of 100 mA to flow, it is necessary to apply a gate-source voltage of about 3.2 V. Since I want it to operate in the saturation region, VDS>=VGS-Vtn. The worst case occurs when the threshold voltage (Vtn) is minimum, which is 1V (datasheet). So: VDS>=3.2-1=2.2V. Therefore, we choose a value for VDS of, for example, 2.5V. As we use a power supply (measured) of about 5.1V (Arduino), the remaining voltage 5.1-2.5=2.6V is distributed equally in the resistors RD and RS. With which, both must be worth RS=RD=(2.6V/2)/100mA=13 ohms. The necessary gate voltage can be obtained as: VG=VGS-VS=3.2-1.3=1.9V. We get this voltage using as RG1=1M and RG2=470k+100k+10k+2*4.7k.

However, when assembling the circuit, the voltage values ​​VGS, VDS and the voltages on the resistors RD and RS are not what they should be. For example, the supply voltage drops all between drain and source and none across RD and RS. I don't know if it's the design that's wrong. Could someone tell me why?

To power the circuit I use four 5V outputs from the Arduino (one specific for more powerful projects) in parallel, so that it can supply the 100mA current.

The image of the designed circuit is as follows:

Answer 1

What you are aiming for is the drain resistor to be at 1.3V. With a Vgs threshold of 2.1V, then the gate voltage should be 2.1+1.3 = at least 3.4V. So what you show clearly won't work at all.

The actual bias value will also depend on the transconductance of your FET, that is, the ratio of a change in input voltage to a change in output current. This varies with the operating condition of the FET. So you'll have to fiddle with the gate bias voltage a bit. I did a quick Falstad sim and came up with something between 3.4 and 3.5V for the bias value, but not using your exact FET model.

Regardless, the repeatability of your circuit isn’t great because it counts on a specific Vgs threshold and transconductance behavior. Manufacturing tolerances for these FET parameters are fairly wide, and are influenced by temperature. In other words, your circuit isn't compensated in any way.

If you add an NPN common-emitter to the sense resistor to create negative feedback you will have better results, and the sense resistor size can be smaller.

Example (simulate it here):

A still better solution is to use an op-amp to sense the current and use that to control the FET gate.

Example (simulate it here):

If you choose an op-amp whose inputs can include GND, the sense resistor can be very small.

Answer 2

Your understanding of biasing is faulty. The typical \$V_{GS(THRESHOLD)}\$ value is 2.1 volts (drain current = 250 μA) and you want 100 mA to flow hence, 1.89 volts is way too low: -

And this means that the MOSFET will be off because, if it begins conducting, the voltage at the source rises positively and shuts down the device due to negative feedback.

If you look at this graph in the data sheet: -

You'll see that you need around typically 3.1 volts of \$V_{GS}\$ to achieve something like what you want. And that naturally means that the gate voltage wrt 0 volts will need to be 3.1 volts plus that dropped across RS (1.3 volts). So, in reality, you'll need a gate voltage of about 4.4 volts typically.

The blue value above of 2.5 volts represent the voltage that is needed across the drain and source to achieve 100 mA drain current (given the drain and collector resistor values) and, as said earlier, that to me looks like a \$V_{GS}\$ of typically 3.1 volts but....

The repeatability between actual MOSFET performance and their data sheet nominal values is also going to disappoint you.

Answer 3

Due to the fact that the gate of the N-FET is at 1.89 V and the datasheet states that gate threshold voltage is between 1 V and 2.5 V, I believe there is a big risk of RS resistor pulling source too high. That way the circuit likely finds an equilibrium where the FET is barely conducting and dropping almost all the voltage over itself. To verify this you could short circuit the RS resistor and see if the circuit works as expected. To counteract this effect you might want to raise gate voltage or reduce value of RS.

Generally N-FET and low side loads is often harder to design.Check out this thread: CMOS: Why is an nMOS transistor a bad conductor of high logic, but a good conductor of low?

Additional comment is that it is not very good to have very high impedance at the gate of a FET, it makes the gate susceptible to EMI.