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I've made a AC-DC step down buck converter that converts 220 VAC to a variable 45 to 70 VDC at 5 to 10 A to charge a Li-Ion battery. I'm currently using ESP32 to drive a MOSFET driver (IR2110) to drive my NMOS placed at the high side of the circuit. The switching frequency is 20 kHz. I also made a crude closed loop control based on current readings (with ACS712 Hall effect Sensor) to increase or decrease the duty cycle. Below you can see my buck converter and gate driver circuit.


Optocoupler and gate driver circuit Fig 1. Optocoupler and gate driver circuit

Buck Converter Circuit Fig 2. Buck converter circuit. (Do note that the current sensor mentioned above is placed at V_OUT)


My current problem is when the buck converter output is more than 1 or 2 A, the NMOS breaks (it acts as a short circuit), even though the NMOS is rated for 600 V and 40 A, as you can see here in the datasheet.

Below you can see the details on the failure

  • I connected a 50 ohm resistor to V_OUT to act as a dummy load to test the voltage and current output of my buck converter circuit. In doing so, the output current will adjust based on my duty cycle.
  • The input voltage is 220 VAC, which then is rectified to 311 VDC (I haven't confirmed its waveform with an oscilloscope, as I don't have access to one which can read such high voltages. Although when probing with a multimeter, its output is near 311 VDC).
  • When I set the duty cycle to 12%, theoretically the output voltage should be near 36 V. But from my observation, the output voltage is 51 V (and the current output readout is 1.02 A). It doesn't stay still at 51 V, but it slowly goes up to 60 V. And not long after that, the voltage reading spiked up to 300 Vand the NMOS is dead.
  • I've already used a heatsink (a 5x5 cm square heatsink) and a desk fan blowing air to it. At 12% duty cycle, the power output should be near 26 Watts (P = V^2/R = 36^2 / 50 = 26 W), so the heat dissipation should not be a problem (I think).

Because I only have a low voltage oscilloscope, I tried connecting 5 V directly to the HVDC node (see Fig 2) to give the system a 5 VDC input, to see the Source-Ground voltage characteristics when switched on or off. There's a bit of ringing (at approximately 20 MHz) and spiking (5 V spikes, in addition to 5V ON voltage) when the NMOS is switched ON or OFF. I've tried various snubber design and component values but I can't seem to remove the ringing and spiking fully. My guess is that when powered from 311 VDC, the spike is also bigger in value, and thus breaking the NMOS. However, I have yet to observe the spike voltage when connected to 220 VAC mains.

I tried to follow ROHM's guide to selecting snubber component values, and a snubber design from Ned Mohan's book Power Electronics, as shown below.

enter image description here Fig 3A (left). Ned Mohan's Snubber Design for low side switch
Fig 3B (right). My snubber design for high side switch


The measured source-ground voltage is shown below

enter image description here
Fig 4. Source - GND transient voltage when no snubber attached. Voltage spike is at 4.64V (cursor B)

enter image description here
Fig 5. Source - GND transient voltage when snubber from fig 3B is attached to the circuit. Voltage spike is 2.9 V (cursor B). I tried varying the capacitor and resistor values (a combination of 10 nF, 100 nF, 200 nF and 10Ω, 100 Ω, 50 Ω) but the waveform seems to not change much.

My questions would be:

  1. Besides the ringing and spiking, are there any more possible reason that can cause said NMOS to fail?
  2. Does the ringing actually harm the NMOS? If not, can I just use an IGBT with 1500 VDC rating to bypass the excess voltage spike?
  3. Are there any mistakes in my circuit design that can cause the NMOS to fail?
  4. If I found a snubber combination that can suppress said spikes and ringing at 5 VDC, will the same combination values work with 311 VDC?

If it helps, the PCB design can be seen below. There are some components that are not shown in Fig 1 or 2, it's just a relay and a discharging resistor. Do note that the relay is not present when the failure happened. enter image description here Fig 6. Top layer of PCB

enter image description here Fig 7. Bottom layer of PCB

enter image description here Fig 8. Prototype layout (only for snubber testing at 5 VDC). I know that soldering the NMOS like that is a huge safety concern, but this setup is only for testing the spikes and ringing I described above with 5 VDC input connected straight to the drain (HVDC node at Fig 2). When the failure happened, the NMOS is soldered straight into the board.

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    \$\begingroup\$ What's your inductor's saturation current rating? \$\endgroup\$
    – John D
    Apr 21 at 14:39
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    \$\begingroup\$ And what's your switching frequency? You might want to include your PCB layout and a photo of your prototype as well as layout can be critical to a successful design. \$\endgroup\$
    – John D
    Apr 21 at 15:09
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    \$\begingroup\$ +1 for a well detailed first question. Welcome! \$\endgroup\$
    – raaymaan
    Apr 21 at 15:27
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    \$\begingroup\$ Your snubber is going to be essentially useless mounted on a breadboard off of the PCB. A snubber has to be connected to the ground plane and switch node with absolute minimum series inductance. Having the FET at the end of long leads is asking for big problems due to source and gate inductance. As a minimum you should clean those things up. \$\endgroup\$
    – John D
    Apr 21 at 21:22
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    \$\begingroup\$ I think that very long and thin traces to the FET gate and from driver to FET source are the cause. Also, transmission of PWM signal through simple optocoupler is a bad idea (it is slow), and it is nearly useless (and dangerous!) because signal and power grounds are joined. At my opinion, direct control of SMPS by MCU is very unreliable, it is safer to use dedicated IC with current and voltage feedback and provide its setpoints by MCU. \$\endgroup\$
    – Vladimir
    Apr 21 at 22:03

5 Answers 5

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My advice is you to get a proper working voltage equipment. All you need is a 10:1 or 100:1 probe. Otherwise you are working on the assumption your test circuit represents the real thing, and that is not always ensured.

One thing I noticed after a quick look at you PCB is how far the regulator is from the mosfet. It should be as close as possible and with traces not changing layers (vias add impedance). You may say 20 kHz is a low frequency and indeed it is, but it affects the on and off edges that you want as sharp and clean as possible.

The fact that with 12% DH you get 51 V puzzles me. That voltage relates to a 16% DH or 8 us ON time, while 12% is 6 us. I would look for those missing 2 us, maybe some software delay? Or it could be some analog delay on the optocoupler, etc. (they are far from instantaneous)

I would say it's a PCB layout problem. Critical connections (basically around the mosfet and sensing) need to be short and straight. I find components too spread apart (inductor, diode, mosfet) especially the driver and sensing connections.

How do MOSFETs fail? Besides the common static values over the maximums, there is the dV/dt failure, typically understood as Vd spikes, but it actually refers to Vds variation (dVds/dt). In your case we can consider Vd fixed but Vs being at the mercy of the inductor and diode after turn off, have you checked that with LTspice? All you need is the models.

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  • \$\begingroup\$ I now already have access to a differential probe, and I can see the voltages if I'm ready to test my circuit again with the proper high voltage input. For now, I think I'm going to solve the spiking problems first. About the missing 2 uS, there's nothing running on the microcontroller except this open-loop PWM control, so maybe it's not from a software delay. And about the 51V output with 12% duty cycle, I think the MOSFET is on the verge of dying due to the spikes, and that's why the voltage keeps rising. Though I'll try measuring the optocoupler output to see the actual duty cycle. \$\endgroup\$
    – Kevin
    May 11 at 18:29
  • \$\begingroup\$ I've run a simulation with a corresponding MOSFET model, but there's seem to be no spikes like in the scope monitor. Although after using a current probe for the oscilloscope, I now know that what's been killing the MOSFETs is the current spikes generated from the main inductor (L1) every time the switch is turns ON an OFF for the first time. From what I saw, the current spikes can reach up to 10 times the output current value. I've now added an RLD snubber in series with the MOSFET to minimize the current spikes. All in all, thanks for your suggestion and new POVs! \$\endgroup\$
    – Kevin
    May 11 at 18:35
  • \$\begingroup\$ @Kevin, current is what kills, yes, and the inductor is what drives current, yes, but bear in mind that an inductor tries to keep the same current flowing, so any current peak I would say is the effect right after the failure, that could be, for example a secondary MOSFET turn-on that would supply 311 V to the inductor and that could trigger a dV/dt failure. All that may happen in ns and unless you have a very expensive scope with GHz bandwidth you might miss them. All guesses what I'm saying, but things to check and better than fiddling with components. Power can be very tricky. \$\endgroup\$
    – Joan
    May 12 at 8:59
  • \$\begingroup\$ At the first turn on, there are 311V across the inductor (Vout = 0) so current will ramp up at a certain rate (no spike in theory). After the first turn off, inductor current will decrease and will be supplied by the diode. In subsequent cycles, because Vout is higher, the inductor will see a lower voltage and current will ramp up slower and reach lower peak values. That is the theory of buck converters. Could you be saturating the inductor? you need it able to handle a current, not only the max DC output but the max peak current in the worst conditions, something like 50A won't be unusual. \$\endgroup\$
    – Joan
    May 12 at 9:06
  • \$\begingroup\$ Sorry for the late reply, but what did you mean by "a secondary MOSFET turn-on"? Currently, my circuit only has one MOSFET that's connected to 311V. \$\endgroup\$
    – Kevin
    May 18 at 4:36
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Your diode D6 is the problem. The datasheet of this historical component says 35V max reverse voltage! You need 400V or more here. The diode either died at the first attempts to start the circuit and vanished. Then there is no regular path for the inductor to drain it's magnetic energy. The other option is, that the diode is still alive and operates as power Z-diode. Then it's a fight fet versus diode and the diode wins it. The current in fet and diode is the same, but the fet has 250V across and the diode 50V. So most of the energy is dissipated in the fet.

These diodes will match here: SDUR3040WT, ER3004PT_T0_00001

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I'm also worried about the optocoupler. Use an >= 1MBit digital coupler here and split up the connection between ESP GND and SMPS GND for your own safety.

Another issue may be, that the voltage across C2 (22uF) may drop too hard to keep the fet fully on. Initially it's fully charged because VOut is zero, but it will only be recharged if D3 is conducting. This time is short at light load and low duty cycle. Your safety resistor R3 is unusual low (1k) and consumes 10mA during fet on time. To me it's not clear that the gate driver voltage is stable during t-on. The IR2110 will not start a new on-time in undervoltage condition, but I think, it will not abort an already running cycle. It is possible that R-On is rising and the fet ends up in a half conducting state with some hundreds watt peak power with danger of oscillation as a consequence of the long source wire. If there is a >10MHz oscillation running, it may not even turn off at all until it's melted.

To my surprise there is no local capacitor on board to stabilize the +12V supply. So the reload path via D1 is very long and inductive, even going through the ESP connection wire! The IR2110 will also miss a cap close to pin 3.

There is no capacitor on board to stabilize the +5V for the IR2110 and the coupler, this is not acceptable. The physical location of a capacitor ist very important, it's not enough to have one on the ESP board.

R5 in your snubber design will have a short life while directly feeding the output from 311V.

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  • \$\begingroup\$ When there's no voltage at the drain (HVDC node in fig 2), my IR2110 output is clean a square wave. However when there's a DC voltage, it's not a clean square wave anymore. Could this be because of an insufficient capacitor value like you said? \$\endgroup\$
    – Kevin
    May 18 at 4:23
  • \$\begingroup\$ About the stabilizing capacitors, yes I currently don't have one for the 12V IR2110 reference. For the 5V stabilizing caps, it's on my other board like you said. I'll try adding those caps near my IR2110 and try again. And about what you said "IR2110 will also miss a cap close to pin 3", can you clarify what you meant? \$\endgroup\$
    – Kevin
    May 18 at 4:26
  • \$\begingroup\$ Pin 3 is the 12V low side driver supply. Well, you don't use the low side output, but you just don't know what the chip internally will do with it. I'm pragmatic in such situations: A cap costs some cents only and having it there, I can be sure that this is not the source of a problem. Life is too short to hunt down things like that.. \$\endgroup\$
    – Jens
    May 18 at 4:34
  • \$\begingroup\$ From your last sentence, it's implied that my snubber topology/placement is not ideal. Do you have any recommendation on what topology should I use? Also, I've monitored the current flow at the Source node (after the NMOS source pin, and before the diode cathode), and there's seems to be a high current spike (5 to 10 times the average current). I've tried using an RLD snubber to reduce the current spike, however it kind of "limits" my output voltage. By that, I mean that when I try to increase the drain voltage, the output voltage stays the same. Do you also have any suggestion for this? \$\endgroup\$
    – Kevin
    May 18 at 4:35
  • \$\begingroup\$ Okay, I'll try soldering some caps in between Pin 3 and GND. If it's relevant, I'm using this reference for my driver circuit (tahmidmc.blogspot.com/2013/01/…). \$\endgroup\$
    – Kevin
    May 18 at 4:39
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This PCB design will not work, even if you think it works. It's an EMI nightmare, and won't be reliable long-term, as various components are likely overstressed due to everything ringing like a bell tower.

One PCB side - top side to make things easiest - should be solely ground. The bottom side should have all the other connections. You'll need to realign the components to minimize current loop areas, and to make it possible to implement the circuit using a 2-layer board with one layer dedicated to a ground plane.

The critical loop areas are:

  1. Gate driver's bootstrap cap through the gate driver chip to the mosfet gate, then source, and back to the driver chip.

  2. C4-Q2-L1-C3 primary loop.

  3. C3-L1-D3 secondary loop.

You should literally draw these loops on the printout of the layout, and estimate their area. The area of high-current loops should be ideally below 1 square inch. The area of the gate driver loop should be 1/4 square inch ideally. The through-hole components of course do you no favors here, but it should be possible to at least close to the target areas with judicious design.

I have no idea what function does the optocoupler serve: it doesn't actually isolate anything, but it does destroy the signal integrity of the PWM waveform for sure.

You probably don't need the bootstrapped high-side gate driver. A basic low-side driver will work fine. The idea is to put ESP32's ground level at the NMOS source. The output voltage can be measured by converting it to a currents that drives a LED-photodiode optocoupler, then using an op-amp to convert the photodiode current to a 0..3V voltage for ESP32's ADC.

I presume that the idea is to have the ESP32 connected via WiFi, so it doesn't matter what exact potential it sits on.

You'd then have a separate ground plane for the ESP32 and the driver circuitry, connected to the NMOS source. The ground plane would be "cut out" from the GND node ground plane.

There are other problems with the circuit design, but other answers mostly cover that.

For diagnosing such circuits, you'll want to integrate various voltage/current buffers, using fast op-amps/differential amplifiers, directly on the board, so that you can then just attach probes to buffered outputs and not worry about the probes adding capacitance/inductance to the circuit. These monitoring circuits will have to be surface mount and a tight layout close to the source of the monitored voltage or current.

Basically, to learn how this works (or not), you'll need to implement instrumentation directly in the design. You can leave it unpopulated for high-volume production, but those components can then be always added for service/maintenance as needed. Ideally, you'd just leave them in - at low volumes (<1000), it makes no difference in product price, as your time has way more impact on the cost.

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  • \$\begingroup\$ To clarify, this board is for development purposes only, to make troubleshooting and measuring currents/voltages easier. It's also made that way to make me add/remove snubbers easily when testing. After I verify the circuit is working, I intend to make the HV loop and control loop closer together. As for the optocoupler, I also ditched it and as of now, only use the TLP250 to drive the MOSFET. \$\endgroup\$
    – Kevin
    Jun 12 at 7:47
  • \$\begingroup\$ Also, thank you for your suggestion for the diagnostics and other aspects of my circuit. Although I have a question, if I don't have access to a busbar for the HV loop, how do I trace the high current lines in one layer? I did so because of the trace is too large to fit beside the MOSFET and diode pins \$\endgroup\$
    – Kevin
    Jun 12 at 7:50
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Turns out, my main inductor (L1) is saturating due to its very high permeability constant. I wound a custom inductor with a permeability factor of 10 with ~200 turns to get 600uH, and the buck converter works as intended.

Although, there's some inconsistency with the driver circuit (heats up and dies randomly), and I ended up changing it to TLP250 for consistent driving capability. I'm not exactly sure why this happened, but from what many people commented on this thread, IR2110 is not suitable for high side driving only

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  • \$\begingroup\$ The layout you have is still an EMI nightmare and should be discarded and redone. If this is an open-source project, I can re-lay the board for you in a couple of hours if you'd like, just to show how a better layout would look. A solid, uninterrupted ground plane is a must. There are multiple blunders in the layout. For example, a conservative design would have the gate driver's output be within 0.5" of the mosfet's gate input terminal, etc. \$\endgroup\$ Jun 11 at 21:35

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