When you pick a STM32F4 chip at random and look at the datasheet, in section 2.2 we see a block diagram of the chip.
We see that the CPU has three (!) buses - labeled I-BUS, D-BUS and S-BUS. All of them go to the "AHB bus matrix" and the D-BUS also goes to some "CCM data RAM".
I searched for "Cortex-M4 S-bus" and found this page from ARM describing the buses which describes the difference between the buses: For addresses lower than 0x20000000, the D-Bus is used for data access and the I-Bus is used for instruction accesses. For addresses 0x20000000 or higher, the S-Bus is used for both instruction and data accesses.
So the processor acts as a Harvard architecture below 0x20000000 and von Neumann above that.
However, if we go back to the chip datasheet, in section 2.2.7 (after the page break) we see a diagram of the AHB bus matrix which interconnects the different buses to different memory components on the chip. We see that the I-Bus and D-Bus have access to the same memory components: Flash memory (via ACCEL), SRAM1, and FSMC Static MemCtl. So by taking a Harvard architecture and then connecting the I and D buses to the same memory, we turn it into what may as well be called a von Neumann architecture. We can assume that each memory region has the same address on all buses where it can be accessed, because otherwise the datasheet would say otherwise. It's convenient that each piece of memory only has one address. It would be possible to connect the processor so that the instruction at 0x00000000 is different from the data at 0x00000000, but the designers of the STM32F405xx did not do that.
There is a slight difference: the "data CCM" memory cannot be used for instructions as it's only attached to the D-bus. Your memory map does not show "data CCM" below 0x20000000 so I guess on your chip this difference does not exist. However there may be other differences between the I-bus and D-bus.