# How to simulate this circuit for common mode voltage effect?

Regarding my previous question and this paper, I wanted to simulate the circuit below to see whether it is rejecting common mode voltage as claimed. The paper says that sharing DAC's Vref with non-inverting node, the common mode voltage variation at Vref will not effect the output:

To try that, I first modeled the DAC and tried the following circuit in LTspice:

But I get the following plots for (Voutp - Voutn) and Vcm; showing that Vcm appears at the output:

Another similar variant of this circuit is as follows(with voltage divider):

And now I removed the ground of the DAC model and voltage divider to the non-inverting input as follows:

And now the output is quiet small:

I couldn't figure out what I am doing wrong. Or is my last try correct way to do this? How can this circuit be simulated in SPICE so that we can see the common mode error is eliminated as claimed?

• Removing the ground will leave an open node, which works sometimes but sometimes introduces numerical instability. Technically there is a fp cap on those nodes but best to also put some resistance on it. Apr 22, 2022 at 18:08
• Does anything change if you use [Opamps]->UniversalOpamp2 instead of the LM324? Apr 22, 2022 at 20:35
• The opamp you're using for the DAC is nothing but a G+(R||C). Apr 23, 2022 at 8:22
• @SteKulov No it didn't make any difference. Im looking for someone to simulate what that paper claims. Apr 23, 2022 at 19:33
• @ty_1917. I'd like to kindly make a suggestion: why not providing a quote, print or formula from the app. note, where it specifically claims that "the common mode voltage variation at Vref will not effect the output:". It may help contributors to focus on that (proving or disproving, maybe). Apr 23, 2022 at 19:37