I have a task to generate a triangular signal with variable amplitude and support.

The figure shows the type of signal and what parameters I want to change (“d” and “o”). Moreover, I need to change the amplitude in a small range (1mV-0.5V.), And the support from 0.5 to 2.5V. enter image description here I implemented this using a microcontroller and its two DAC outputs and an additional op-amp circuit. The first output of the DAC generates rectangular pulses with adjustable amplitude. The second output of the DAC generates a constant voltage with adjustable amplitude. Then all this is sold at the op-amp, where one stage works as an integrator, and the second how to repeat, and then I raise the triangular signal to the level I need. Here is the diagram: enter image description here When I assembled this circuit and checked. I saw that the signal received at the output has noise, especially when I need to form a triangular signal with an amplitude of tens of millivolts. I'm using an STM microcontroller, maybe it has a rather noisy DAC. The frequency of the triangular signal is 1kHz. Power supply of the microcontroller and op-amp 3.3V.

I need to get a triangular signal, with a frequency of 1kHz, with the possibility of amplitude and support adjustment and minimal noise. How can I reduce the noise in this circuit, or how can I redesign the circuit to achieve minimal output noise?

P.S. Maybe I'm doing it all wrong and I should implement it somehow differently?

Here is the part of the PCB that is responsible for the formation of a triangular signal: enter image description here The op amp and microcontroller pins (VDDA and Vref) are powered by a low noise linear regulator. R20 is not installed. I also tried to apply a signal of several volts from the DAC1 output and increase the capacitance of the capacitor in the integrator feedback circuit in order to reduce noise, but this did not change much.

  • \$\begingroup\$ Probing errors can induce noise. Impedance control can attenuate crosstalk if known. Choice of low parasitic inductive probe ground length can induce noise > 20MHz. Choice of 0V=Agnd can also affect SNR. A differential approach needs to factor gain tolerance errors (f) and crosstalk with f-3db=0.35/Tr \$\endgroup\$ Commented Apr 22, 2022 at 19:16
  • 2
    \$\begingroup\$ If you're concerned about noise in the mV range, we'll need to see your PCB layout as well--that has a big impact on how much noise is picked up from ambient radio waves, for instance. \$\endgroup\$
    – Hearth
    Commented Apr 22, 2022 at 19:18
  • \$\begingroup\$ In particular, noise on the grounded terminal of the 1uF capacitor can be directly transmitted to the output. If you want more help, please describe the noise spectrum as well as the layout. \$\endgroup\$ Commented Apr 22, 2022 at 19:32
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    \$\begingroup\$ Create the signal at some volts amplitude, and attenuate to mV. \$\endgroup\$
    – user16324
    Commented Apr 22, 2022 at 20:11
  • \$\begingroup\$ As @user_1818839 pointed out, Why don't use one DAC for creating the triangular wave, and a "multiplying DAC" ( or "attenuator" ) for choosing "amplitude", and then add one offset with the second DAC? Differentiating a signal is not really the best way to use it... \$\endgroup\$
    – Antonio51
    Commented Apr 22, 2022 at 20:17

1 Answer 1


One idea on how to implement differently –

Since you have a microprocessor you could consider creating the triangle there in the first place.

Now, with a 12-bit DAC and 3.3V supply the ls bit quantization is only 3.3/4096 = 0.8mV so won’t be able to get a decent 1mV triangle.

But your max output target is only 0.5V pk-pk. The DAC is capable of generating 3.3V pk-pk and you should take advantage of that to maximize signal to noise ratio. So, you’d generate a max 3.3V triangle from the DAC then attenuate by 6.6:1 to achieve the desired 0.5V output.

Now instead of needing to create a 1mV signal from your DAC you just need to generate a 6.6mV signal, because it will be attenuated to 1mV by the analog circuit. With 0.8mV steps you’d now have 8 quantization levels to generate your lowest level signal. If this is acceptable then this scheme should work and avoid the fussiness of the analog integrator scheme.

Your DC offset circuit is fine but you don’t need the 10K/1uF on the top opamp – they’re not doing anything.

enter image description here

  • \$\begingroup\$ I don't quite understand your idea. You propose to increase the input voltage by 6.6 times, but it is not clear how it will be weakened back? And at the same time, I don’t understand at all how, while maintaining a frequency of 1 kHz, I can generate different amplitudes of 1mV-0.5V \$\endgroup\$
    – red15530
    Commented Apr 24, 2022 at 18:03
  • \$\begingroup\$ The signal is weakened back in the analog domain by the lower opamp, whose gain is R/6.6R. You generate your waveform in firmare by writing samples to your DAC, each of which can be any value from 0V to 3.3V, with a resolution of 0.8mV. Let’s say your sample rate is 16kHz – that means you will generate 16 samples per 1kHz period, 8 going up the triangle and 8 coming back down. The steps between those samples will dictate the amplitude. Your min pk-pk amplitude will be when your step size is 1, (0.8mV), 8*0.8 = 6.4mV. Max will be when step size is 4096/8 = 512, 8*512*0.8 = 3300mV. \$\endgroup\$
    – td127
    Commented Apr 25, 2022 at 0:02

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