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I have these two xor logic diagrams, they seem to work the same on inputs which are not even, but what is the difference between them? What is the purpose of it and which one would be faster?

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There does not appear to be any logical difference.

The second will be faster, because there are only two XOR-gate delays between inputs and outputs, as opposed to three.

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  • \$\begingroup\$ The second one is not faster per se, it is equally fast in regard to all inputs. The first one will react faster to the lowest input on the diagram. \$\endgroup\$
    – fraxinus
    Apr 23, 2022 at 21:49
  • \$\begingroup\$ @fraxinus You're right. It has been a long week. \$\endgroup\$ Apr 23, 2022 at 21:50
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    \$\begingroup\$ @fraxinus The second one is faster in the worst case among all inputs, which is generally what matters. \$\endgroup\$
    – Nayuki
    Apr 23, 2022 at 22:05
  • \$\begingroup\$ @Nayuki what is the worst case depends on what the rest of the circuit does. E.g. you can have a race condition because a certain signal propagates too fast or too slow. \$\endgroup\$
    – fraxinus
    Apr 23, 2022 at 22:10
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    \$\begingroup\$ Naming the inputs A, B, C, and D from top to bottom: The top circuit will respond in 3 gate prop times to changes in A or B, 2 gate props to changes in C, and 1 to changes in D. The bottom circuit will respond in 2 gate prop times to changes in any input. \$\endgroup\$ Apr 24, 2022 at 0:04

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