I have a set of LED light strips (LEDs + resistors integrated) that I want to control with MCU GPIO outputs. The MCU outputs 3V3 signals.

I have tested the IRBL8721 Power MOSFET and also the IRFZ44 (without the microcontroller) at a variety of gate voltages and they both carry the load just fine (each light strip is 1--2A current draw). I noticed however that at V_gs of 2.8V or so, the IRBL8721 gets into the linear range and starts to heat up dramatically.

This application will be powered from a 12V deep cycle battery (with an appropriate switching regulator to power the MCU) that will be recharged by solar panels. While I'm planning to engineer in some headroom, it is not impossible that the device will run down the battery overnight and start to brown out. So I'm nervous about driving the IRBL8721 directly from the GPIO, in case that signal starts to dip down into the 2.8--3.0V range, which would pull it into the linear region and may damage the FET or the PCB. The IRLZ44 has a lower Vgs(th) so is more tolerant of these conditions, but it's also 3x the cost.

It occurred to me that a PMOS transistor (active low) controlling the gate voltage on the power FET might solve the problem by ensuring the Power FET is either experiencing 0V or something well into the saturation region like 9V. (By the time that sags to 2.8V, the MCU has likely already shut down.)

Does this circuit do what I want?

A PMOS transistor, driven by GPIO, controlling an NMOS power transistor that switches on an LED load

I've gotten myself a bit confused with PMOS transistors with the flipped source/drain vs how they're oriented in NMOS. The TP2104 has VGS(th) of -2 to -1V. Does that reference the absolute common ground shared between the 3V3 and 12V0 rails? Or is that relative to the drain? (which I think is effectively always at +12V minus Rds(on)*I -- kept tiny by large R3 & R4 -- when it's active?)

  • \$\begingroup\$ PMOS vs NMOS follows the same convention as NPN vs PNP bipolars - the gate needs a voltage applied relative to the source, positive for n-channel and negative for p-channel. \$\endgroup\$
    – Frog
    Apr 23, 2022 at 21:49
  • \$\begingroup\$ WHere does 3.3V come from? 12V??. Yes your Pch gate drive is always On \$\endgroup\$ Apr 23, 2022 at 22:58
  • \$\begingroup\$ @TonyStewartEE75 a switching regulator (not pictured) will take 12Vin and produce the 3V3 needed for the MCU. \$\endgroup\$ Apr 24, 2022 at 0:22
  • \$\begingroup\$ If you want to use a low side switch with specified working range of Vgs range for Vdd=3.3 and and specified current range, with a maximum Pd of say < 0.1W over the entire range, all you need is a single Nch FET to achieve that and there are thousands of solutions direct drive down to 2V with "logic level" FETs and Vt or Vgs(th) = ~ 1V. Why complicate this? \$\endgroup\$ Apr 24, 2022 at 13:50

2 Answers 2


I'll have to simulate it to be sure, but it seems to me like you're just transferring the same burden onto the PMOS. Since its gate is held at a constant voltage of 3.3V, when the battery voltage hits 4-5V (depending on Vth) the PMOS is now operating in the triode region. True, your NMOS might have a lower drain current then because higher PMOS resistance means lower gate voltage at Q2. But this is probably what I'd have done.

The idea here is that your opamp behaves as a comparator, comparing the voltage of the battery with a steady 3.3V (that I presume is being generated by an LDO, so it'll be steady till a battery voltage of 4.3V or so. I think. Best to check how your LDO behaves around dropout). When the battery voltage falls below 3.3V, the gate of the NMOS is turned off.

Did a quick LTSpice simulation, works just as expected. The Spice file for your NMOS was easy to find, but the opamp I put in here was a random one from the LTSpice library so you might have to find one that works for you. You can see the gate voltage (red) hits 0V and so the current (cyan) also hits 0mA when the battery voltage (green) intersects the 3.3V line (blue). Won't have to worry about any battery drainage or heating after this point.

Just a reply to your last paragraph -- the -2 to -1 is from VG to VS. The way you've connected your PMOS, that's (3V3 - battery voltage). Not battery voltage minus current*Rds(on), because for PMOS you usually connect the source to a higher voltage than the drain. So your source is at +12V and drain is connected to R3. Remember that the body terminal is always connected to the source for both NMOS and PMOS, but the directions of the body diodes are reversed (source->drain for NMOS, drain->source for PMOS). And for PMOS, the operating region equations are the exact same as for NMOS with the quantities becoming negative but the greater than/lesser than symbol staying the same -- this helps me remember how PMOS transistors work, hope it helps.

  • \$\begingroup\$ Also, in case this doesn't work for you, I believe these kind of circuits are called supervisor circuits. You might be able to find more sophisticated circuits online since this was just a rudimentary one I came up with. Or just google "undervoltage protection" and see what you get. Might even find dedicated ICs to do the job, if you have the budget for it. \$\endgroup\$
    – Vortex123
    Apr 23, 2022 at 21:44
  • \$\begingroup\$ Hi @Vortex123, this is incredibly thorough, thank you! I think I was maybe unclear though. The 3V3 GPIO signal needs to be able to turn on and off; I need to switch the LED. The opamp example here just monitors power supply voltage. Also the sole battery is @ 12V so it will have probably ceased producing power long before it his the 4--5V point. I think maybe the open-ended way to phrase the question I should have asked is "How do I switch a low-amp small-signal at Vcc=12V using a gate voltage that has a range of 0--3.3V" ? \$\endgroup\$ Apr 24, 2022 at 0:27
  • \$\begingroup\$ Oops -- seems like I misunderstood the question. I thought the battery running down caused your power MOSFET to overheat. Though your clarification makes me curious about some other things. Why would your gate voltage coming from a MCU GPIO go below 3.3V? They're usually steady. And MOSFETs operate in triode region when Vds (not Vgs) is not high enough. Are you sure the region of operation is what's causing your heating issues? \$\endgroup\$
    – Vortex123
    Apr 24, 2022 at 14:07
  • \$\begingroup\$ Anyways, if you want a higher voltage at your NMOS gate, you can just put a charge pump before it. They're a standard type of circuit, pretty easy to implement, and you control them with PWM from a MCU pin. There are also modifications to the circuit that let you switch off the gate voltage if you want to, should be able to find them online. \$\endgroup\$
    – Vortex123
    Apr 24, 2022 at 14:07
  • \$\begingroup\$ My initial tests involved setting Vgs with an R1/R2 divider from bench Vcc rather than the MCU, Vgs verified with a multimeter, so I'm positive that Vgs undervoltage causes overheating. I'm not certain if MCU Vout would dip but I'm trying to failure-proof a system that is likely to battery exhaustion. If the last 20 minutes of battery life causes voltage drop across the board, I don't want to burn out the MOSFETs or PCB, and I think 20 minutes of pushing 2 amps thru a half-closed gate might do that. So trying to engineer for reliability. \$\endgroup\$ Apr 25, 2022 at 16:46

After some more research I figured out the part I need -- instead of another MOSFET I think I need to use a low-side gate driver like the IXDI602. That'll respond cleanly to the 0.8V / 3.0V logic-level input signals and in response drive the full 12V rail voltage to the Power MOSFET's gate.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.