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Often I see the following circuit (example 1.), e.g. using an additional gate of an NAND gate to invert a signal when using only one 74xx00 CMOS IC with 4 x 2-NAND gates:

schematic

simulate this circuit – Schematic created using CircuitLab

Wouldn't it be better if only one input of the additional NAND element is connected?

I think then there would be only one instead of two transitions at the inputs of the second gate. Possibly the first example could cause problems and cost more cross current during switching. At all, if you connect not only two but even more inputs together (e.g. with quad inputs, etc.)...

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    \$\begingroup\$ the distances and tolerances involved are far smaller / shorter than what these 74 logic family ICs are used for; for all practical matters, both inputs of NAND2 in your upper example switch the same instant. Your lower approach introduces VCC noise into your system. I don't know whether that's better! \$\endgroup\$ Apr 23, 2022 at 20:15
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    \$\begingroup\$ @MarcusMüller I didn't thought about introducing noise into my system when connecting inputs to VCC. I will think about it. In the meantime I found an article at allaboutcircuits.com/textbook/digital/chpt-3/gate-universality where it is written that for CMOS common input terminals decreases the switching speed of a gate because of increased input capacitance. \$\endgroup\$ Apr 23, 2022 at 20:38
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    \$\begingroup\$ It definitely does! But again, compare that to the driving capabilities of the NAND1 \$\endgroup\$ Apr 23, 2022 at 20:48

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Perhaps, but the power consumption for board-level components like 74HCxx logic families, is dominated by pin and trace capacitances, and leakage currents perhaps. Such a concern might be relevant for monolithic design (where the internal gates dominate -- note that 74HC is designed with input and output buffers, the internal gates are a small part of total dissipation), but is down in the noise for board-level design.

Another issue is timing delays, which might not match between the two inputs, so could be optimized that way; but the datasheet won't tell you which, if indeed they differ at all, and not only that, but the worst-case timing constraints in the datasheet are rather awful (process limits I think, not so much representative of average +/- some variance), so it's hard to do much of any design with close to average timing this way.

So, given available data/constraints, it doesn't matter; or, the amount to which it does, is so small not to matter, perhaps outside some rare use cases.

Tim

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