How can I build a current controlled 50% duty cycle oscillator from two CMOS inverters?

Question

I am in need of a current controlled audio range (output around 1000 Hz) oscillator/multivibrator circuit. To make the result sound nice, I want to oscillator to have a 50% or near 50% duty cycle. Previously I've used a current-controlled 555-based circuit whose output I passed into a T-Flipflop to get a 50% duty cycle. But as I have now redesigned the circuit to eliminate a part, there no longer is a free T-Flipflop left to halve the frequency.

How can I build a current-controlled oscillator with the following parameters?

• operating frequency range around 500 Hz to 2000 Hz
• works with inputs of 80 µA to 250 µA (does not need to map to the range above)
• the current comes from a current mirror which I can attach either to VCC or GND
• works with 3V supply voltage, ideally down to 2.5V-ish
• low power consumption (operated by a CR2032 cell)
• 50% or near 50% duty cycle
• built from as few extra parts as possible

I have four inverters of a 74HC04 hex inverter chip left over which I could use for this. I fiddled with a two-inverter multivibrator, but I wasn't able to find a way to find a way to make its frequency configurable without sacrificing the 50% duty cycle.

Two of these four inverters are needed to drive a piezo speaker from the oscillator as a kind of bridged amplifier, but it might be possible to integrate these into a multivibrator design somehow instead of just driving the two inverters from the oscillator.

I also tried using a TLC556 (CMOS dual 555) where one is in astable mode, triggering the second one in monostable mode where both have their frequency controlled by outputs of the same three-way current mirror and the monostable 555 circuit has half the frequency, but matching the parts such that it really works out to 50% seems tricky to get right. It might also work to use one of the two 555 circuits as a T-flipflop, but I wasn't able to find a way to do so.

Any ideas?

Answer 1

After fiddling with this for a few days, I came up with the following circuit:

^{simulate this circuit – Schematic created using CircuitLab}

Here V1 is the logic voltage source and D2, D4 are the internal clamping diodes of the inverters. The principle of operation is as follows: initially both capacitors are discharged and the two inverters assume a random configuration with one output high and the other low. Let's say NOT1's output is high and NOT2's output is low.

The current source then charges C1 until the input voltage of NOT1 rises above the threshold, causing it two switch. As C2 is discharged, NOT2 will switch too. Now C1 is pulled high by NOT2 and is thus rapidly discharged back to VCC through D2, returning the circuit back to the original state but with outputs flipped.

The max frequency is bounded by how fast the capacitors can be discharged with no lower bounds. If the current source is disabled, oscillation ceases. If C1 and C2 have matched capacity, I expect the duty cycle to be 50%. Other duty cycles can be achieved by varying the ratio of capacities.

The frequency is described by 5 parameters: the current \$I\$, capacities \$C_1\$ and \$C_2\$, the voltage drop \$U_D\$ of diodes D2 and D4, and the high level threshold voltage \$U_H\$ of the inverters.

The multivibrator changes state once one of the capacitors is charged from \$U_D\$ to \$U_H\$. Using the law \$CU=It\$, this time is described for \$C_1\$ by

$$t_1={C_1(U_H-U_D)\over I}$$

and hence the oscillation frequency is:

$$f={I\over(C_1+C_2)(U_H-U_D)}$$

It seems to work well in practice. The noise and spikes are due to me measuring at the speaker pin, there's no such noise when I measure the logic outputs (but I forgot to take a picture of that).

The duty cycle is not at 50% due to parts variance in the capacitors. One has 92 nF, the other 102 nF. In the final build I'll probably select matching capacitors.