I am wondering how can I verify that I am getting the noted effective bit resolution?
This is a very cheap and very good DC test I have used on all the ADC/DAQ systems I have ever brought into life. It's not 'calibration' as such, which requires very expensive hardware, but it will tell you whether you have any missing codes, what your differential linearity is, and what your real resolution and noise level is.
It is totally passive, so it's as low noise as you can get. No instrumentation noise, no power supply noise, no ground loops, the only noise you're going to see is the noise of your ADC itself.
simulate this circuit – Schematic created using CircuitLab
Charge C1 to some suitable voltage, and let it discharge into R1. For verifying no missing codes and differential linearity, it doesn't really matter whether the discharge is dominated by the DAQ input current (maybe linear), dominated by R1 (exponential), or a mix of both. Choose R1 and C1 to give you many (10s to 1000s) of readings per expected resolution step, and write a program to analyse what you get. If you use a big electrolytic, relaxation or reforming currents may confound your predictions of what should happen to the voltage, at least until it's settled down, however it will be smooth and zero noise. Plastic caps will be more predictable.
Your two pole SW2 could be a plug and socket, to allow you to mount the components in a small shielded box right at the DAQ terminals, for minimal RF/mains hum pickup without even the switch-isolated wires to V1 contaminating anything. Repeat the experiment with the components further away from the DAQ, to see whether your cabling is picking anything up.