0
\$\begingroup\$

Here is my custom IP component. It has an AXI4 slave bus on one end and a simpler custom bus on the other end. It serves as a bridge function between the two. I am trying to find a way to package this RTL module so Vivado understands that it has an AXI4 and a custom bus on it so I don't have to manually connect every single connection on this component.

enter image description here

Intel Quartus Platform Designer provides a very neat way to create IP for use in their systems. Microsemi Libero SoC SmartDesign also has a neat way to do it. However, I am not able to track down how to do this simple task in Xilinx Vivado.

I briefly attempted the "Create and Package New IP..." and "Create Interface Definition..." but they are not intuitive and give impression that they are not designed for what I am trying to achieve.

What resource can I use to solve this problem? There are a few more modules like this that have AXI4 or some other bus along with discrete signals. I am not sure how to proceed with this.

\$\endgroup\$

1 Answer 1

0
\$\begingroup\$

"Create and Package New IP" is definitely overkill if you just want tidy grouping of intetface signals in the block design diagram.

"Create Interface Definition" is for when you want to define a new custom interface, but as you can imagine the various AXI variants are already defined in vivado.

If you want vivado to group your signals properly you have two options as explained here:

  • Use default naming for signals, so for a slave interface s_axi_<signame> and for a master m_axi_<signame>

  • Use the (xilinx-specific) X_INTERFACE_INFO attribute in your source. For example for your i_s_axi_awaddr signal:

     ATTRIBUTE X_INTERFACE_INFO : STRING;
     ATTRIBUTE X_INTERFACE_INFO of i_s_axi_awaddr: SIGNAL is "xilinx.com:interface:aximm:1.0 i_s_axi_awaddr AWADDR";
    

The second solution is very tedious and also adds quite some clutter to your sources, so I would suggest sticking to the first option.

\$\endgroup\$
4
  • \$\begingroup\$ So by clutter you mean all those VHDL attribute lines? \$\endgroup\$
    – gyuunyuu
    Commented Jun 10, 2022 at 13:12
  • \$\begingroup\$ Yes, but it's just a personal preference \$\endgroup\$
    – J.W.
    Commented Jun 11, 2022 at 19:23
  • \$\begingroup\$ Your point about the "xilinx.com:interface:aximm:1.0" is actually quite helpful. However, what if I have created a custom interface and put it into my repository. Is it possible to use the VHDL attributes for that too? \$\endgroup\$
    – gyuunyuu
    Commented Jun 12, 2022 at 10:12
  • 1
    \$\begingroup\$ Never tried with a custom interface, but if it is defined in the project I don't see why it shouldn't. \$\endgroup\$
    – J.W.
    Commented Jun 13, 2022 at 8:46

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.